32-bit words
28-bit literals

 OP  DATA
┌──┐┌──────────────────────────┐
00000000000000000000000000000000

0000 | LDI | load immediate 
0001 | LDR | load register
0010 | MOV | move accumulator to register
0011 | SAV | save accumulator to memory
0100 | ADD | add
0101 | SUB | subtract
0110 | NOT | not
0111 | IOR | inclusive or
1000 | AND | and
1001 | XOR | exclusive or
1010 | JMP | jump unconditional
1011 | JNZ | jump not zero
1100 | JEZ | jump equal zero
1101 | JLZ | jump less than zero
1110 | JGZ | jump greater than zero
1111 | HLT | halt

load_immediate         : LDI literal
load_register          : LDR register
move_accumulator       : MOV register
save_accumulator       : SAV address
add                    : ADD register
subtract               : SUB register
not                    : NOT empty_literal 
inclusive_or           : IOR register
and                    : AND register
exclusive_or           : XOR register
jump_unconditional     : JMP address
jump_not_zero          : JNZ address
jump_equal_zero        : JEZ address
jump_less_than_zero    : JLZ address
jump_greater_than_zero : JGZ address
halt                   : HLT empty_literal

literal       : [0,1] * 28
register      : ([0] * 25) + ([0,1] * 3)
empty_literal : [0]   * 28
next_word     : [0,1] * 32
address       : ([0] * 20) + ([0,1] * 8)