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Name		Name	Last commit message	Last commit date
parent directory ..
Vitis-Embedded-Software-Debugging		Vitis-Embedded-Software-Debugging
debuggable-fsbl		debuggable-fsbl
sw-profiling		sw-profiling
README.md		README.md

README.md

Outline

简体中文 | 日本語

Embedded Design Tutorials

Debugging

Tutorial	Description
Creating a Debuggable First Stage Boot Loader	First Stage Boot Loader (FSBL) can initialize the SoC device, load the required application or data to memory, and launch applications on the target CPU core.
Software Profiling Using the Vitis Software Platform	Enable profiling features for the standalone domain or board support package (BSP) and the application related to AXI CDMA.
Vitis Embedded Software Debugging Guide	This guide provides specific examples of embedded software debug situations and explains how the various Xilinx debug features can help.

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