digitalClock/DevelopmentIterations at main · kylemath/digitalClock · GitHub

Name		Name	Last commit message	Last commit date
parent directory ..
V0		V0
V1-2		V1-2
V3		V3
V4		V4
V5		V5
firmwareV2_SingleDigitTest		firmwareV2_SingleDigitTest
firmwareV3.5_PublishSingleDigitsSix		firmwareV3.5_PublishSingleDigitsSix
firmwareV3_PublishSingleDigits		firmwareV3_PublishSingleDigits
firmwareV4_Publish4Digit		firmwareV4_Publish4Digit
firmwareV5_Publish6Digit		firmwareV5_Publish6Digit
v10_6Digits		v10_6Digits
v11_6Digits		v11_6Digits
v12_6Digits_Publish6Digit		v12_6Digits_Publish6Digit
v6		v6
v7_PublishSingleDigits		v7_PublishSingleDigits
v8_combined		v8_combined
v9_horizontal_Publish4Digit		v9_horizontal_Publish4Digit
3d-Diagram-Plot.py		3d-Diagram-Plot.py

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