Part of the arm64 port.

x86 forces a wedged spawn down with an NMI per APIC ID (mk_force_stop_cpu(), mk_stop_nmi_callback). PSCI has no "stop another CPU" call, so arm64 needs an in-band mechanism. Implement in this preference order, selected at runtime:

1. SDEI: SDEI_EVENT_SIGNAL(event 0, target MPIDR) is firmware-delivered and runs the target kernel's handler even with DAIF masked. The spawn registers a private event-0 handler at boot that calls psci_ops.cpu_off(). Requires CONFIG_ARM_SDE_INTERFACE and TF-A with SDEI (servers; QEMU virt with TF-A).
2. Pseudo-NMI SGI (irqchip.gicv3_pseudo_nmi=1): reuse the IPI_CPU_STOP_NMI shape with a multikernel handler that calls cpu_off(); reaches CPUs "masked" at PMR level.
3. Plain SGI: last resort, cannot reach a CPU spinning with DAIF.I set. Log that force-halt is best-effort.

• mk_arch_register_force_stop() (renamed from mk_register_stop_nmi_handler()) returns -ENODEV when none is usable; graceful shutdown keeps working.
• mk_force_stop_cpu(mpidr) dispatches on the selected mechanism.
• Completion = AFFINITY_INFO(mpidr) == OFF for every instance CPU (mk_instance_settle_halted()).
• Filter foreign stop events the way x86 does in smp.c / reboot.c.