Commit 2defaaf
deps: V8: cherry-pick 6ea594ff7132
Original commit message:
[riscv] Skip check sv57 when enable pointer compress
Change-Id: I4332d3849d113af105630c0e20cd2b5e3deb9392
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5430889
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#93244}
Refs: v8/v8@6ea594f
PR-URL: #53412
Reviewed-By: Jiawen Geng <technicalcute@gmail.com>
Reviewed-By: Michaël Zasso <targos@protonmail.com>
Reviewed-By: Richard Lau <rlau@redhat.com>
Reviewed-By: Marco Ippolito <marcoippolito54@gmail.com>
Reviewed-By: Rafael Gonzaga <rafael.nunu@hotmail.com>
Reviewed-By: Luigi Pinca <luigipinca@gmail.com>1 parent f9075ff commit 2defaaf
2 files changed
Lines changed: 18 additions & 20 deletions
| Original file line number | Diff line number | Diff line change | |
|---|---|---|---|
@@ -36,7 +36,7 @@ | |||
| 36 | 36 | ||
| 37 | 37 | # Reset this number to 0 on major V8 upgrades. | |
| 38 | 38 | # Increment by one for each non-official patch applied to deps/v8. | |
| 39 | - 'v8_embedder_string': '-node.13', | ||
| 39 | + 'v8_embedder_string': '-node.14', | ||
| 40 | 40 | ||
| 41 | 41 | ##### V8 defaults for Node.js ##### | |
| 42 | 42 | ||
| Original file line number | Diff line number | Diff line change | |
|---|---|---|---|
@@ -83,10 +83,12 @@ void CpuFeatures::ProbeImpl(bool cross_compile) { | |||
| 83 | 83 | base::CPU cpu; | |
| 84 | 84 | if (cpu.has_fpu()) supported_ |= 1u << FPU; | |
| 85 | 85 | if (cpu.has_rvv()) supported_ |= 1u << RISCV_SIMD; | |
| 86 | + #ifdef V8_COMPRESS_POINTERS | ||
| 86 | 87 | if (cpu.riscv_mmu() == base::CPU::RV_MMU_MODE::kRiscvSV57) { | |
| 87 | 88 | FATAL("SV57 is not supported"); | |
| 88 | 89 | UNIMPLEMENTED(); | |
| 89 | 90 | } | |
| 91 | + #endif | ||
| 90 | 92 | // Set a static value on whether SIMD is supported. | |
| 91 | 93 | // This variable is only used for certain archs to query SupportWasmSimd128() | |
| 92 | 94 | // at runtime in builtins using an extern ref. Other callers should use | |
@@ -1086,25 +1088,21 @@ void Assembler::GeneralLi(Register rd, int64_t imm) { | |||
| 1086 | 1088 | ||
| 1087 | 1089 | void Assembler::li_ptr(Register rd, int64_t imm) { | |
| 1088 | 1090 | base::CPU cpu; | |
| 1089 | - if (cpu.riscv_mmu() != base::CPU::RV_MMU_MODE::kRiscvSV57) { | ||
| 1090 | - // Initialize rd with an address | ||
| 1091 | - // Pointers are 48 bits | ||
| 1092 | - // 6 fixed instructions are generated | ||
| 1093 | - DCHECK_EQ((imm & 0xfff0000000000000ll), 0); | ||
| 1094 | - int64_t a6 = imm & 0x3f; // bits 0:5. 6 bits | ||
| 1095 | - int64_t b11 = (imm >> 6) & 0x7ff; // bits 6:11. 11 bits | ||
| 1096 | - int64_t high_31 = (imm >> 17) & 0x7fffffff; // 31 bits | ||
| 1097 | - int64_t high_20 = ((high_31 + 0x800) >> 12); // 19 bits | ||
| 1098 | - int64_t low_12 = high_31 & 0xfff; // 12 bits | ||
| 1099 | - lui(rd, (int32_t)high_20); | ||
| 1100 | - addi(rd, rd, low_12); // 31 bits in rd. | ||
| 1101 | - slli(rd, rd, 11); // Space for next 11 bis | ||
| 1102 | - ori(rd, rd, b11); // 11 bits are put in. 42 bit in rd | ||
| 1103 | - slli(rd, rd, 6); // Space for next 6 bits | ||
| 1104 | - ori(rd, rd, a6); // 6 bits are put in. 48 bis in rd | ||
| 1105 | - } else { | ||
| 1106 | - FATAL("SV57 is not supported"); | ||
| 1107 | - } | ||
| 1091 | + // Initialize rd with an address | ||
| 1092 | + // Pointers are 48 bits | ||
| 1093 | + // 6 fixed instructions are generated | ||
| 1094 | + DCHECK_EQ((imm & 0xfff0000000000000ll), 0); | ||
| 1095 | + int64_t a6 = imm & 0x3f; // bits 0:5. 6 bits | ||
| 1096 | + int64_t b11 = (imm >> 6) & 0x7ff; // bits 6:11. 11 bits | ||
| 1097 | + int64_t high_31 = (imm >> 17) & 0x7fffffff; // 31 bits | ||
| 1098 | + int64_t high_20 = ((high_31 + 0x800) >> 12); // 19 bits | ||
| 1099 | + int64_t low_12 = high_31 & 0xfff; // 12 bits | ||
| 1100 | + lui(rd, (int32_t)high_20); | ||
| 1101 | + addi(rd, rd, low_12); // 31 bits in rd. | ||
| 1102 | + slli(rd, rd, 11); // Space for next 11 bis | ||
| 1103 | + ori(rd, rd, b11); // 11 bits are put in. 42 bit in rd | ||
| 1104 | + slli(rd, rd, 6); // Space for next 6 bits | ||
| 1105 | + ori(rd, rd, a6); // 6 bits are put in. 48 bis in rd | ||
| 1108 | 1106 | } | |
| 1109 | 1107 | ||
| 1110 | 1108 | void Assembler::li_constant(Register rd, int64_t imm) { | |
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