Commit a1b73fe
authored
deps: V8: cherry-pick 2abc61361dd4
Original commit message:
Fix scratch registers passed to mtvsrdd
`ra` cannot be r0 as it will be interpreted as Operand(0)
Change-Id: Idce58191f9d3578dc91dc4aa3872a0bf2939d8b3
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/6936113
Commit-Queue: Milad Farazmand <mfarazma@ibm.com>
Reviewed-by: Junliang Yan <junyan1@ibm.com>
Cr-Commit-Position: refs/heads/main@{#102388}
Refs: v8/v8@2abc613
PR-URL: #60177
Refs: nodejs/undici#4530
Reviewed-By: Colin Ihrig <cjihrig@gmail.com>
Reviewed-By: Michaël Zasso <targos@protonmail.com>1 parent a2f088d commit a1b73fe
4 files changed
Lines changed: 7 additions & 3 deletions
File tree
- deps/v8/src
- codegen/ppc
- compiler/backend/ppc
- wasm/baseline/ppc
| Original file line number | Diff line number | Diff line change | |
|---|---|---|---|
@@ -38,7 +38,7 @@ | |||
| 38 | 38 | ||
| 39 | 39 | # Reset this number to 0 on major V8 upgrades. | |
| 40 | 40 | # Increment by one for each non-official patch applied to deps/v8. | |
| 41 | - 'v8_embedder_string': '-node.8', | ||
| 41 | + 'v8_embedder_string': '-node.9', | ||
| 42 | 42 | ||
| 43 | 43 | ##### V8 defaults for Node.js ##### | |
| 44 | 44 | ||
| Original file line number | Diff line number | Diff line change | |
|---|---|---|---|
@@ -3981,6 +3981,7 @@ void MacroAssembler::I64x2Mul(Simd128Register dst, Simd128Register src1, | |||
| 3981 | 3981 | if (CpuFeatures::IsSupported(PPC_10_PLUS)) { | |
| 3982 | 3982 | vmulld(dst, src1, src2); | |
| 3983 | 3983 | } else { | |
| 3984 | + DCHECK(scratch1 != r0); | ||
| 3984 | 3985 | Register scratch_1 = scratch1; | |
| 3985 | 3986 | Register scratch_2 = scratch2; | |
| 3986 | 3987 | for (int i = 0; i < 2; i++) { | |
@@ -4333,6 +4334,7 @@ void MacroAssembler::I8x16BitMask(Register dst, Simd128Register src, | |||
| 4333 | 4334 | if (CpuFeatures::IsSupported(PPC_10_PLUS)) { | |
| 4334 | 4335 | vextractbm(dst, src); | |
| 4335 | 4336 | } else { | |
| 4337 | + DCHECK(scratch1 != r0); | ||
| 4336 | 4338 | mov(scratch1, Operand(0x8101820283038)); | |
| 4337 | 4339 | mov(scratch2, Operand(0x4048505860687078)); | |
| 4338 | 4340 | mtvsrdd(scratch3, scratch1, scratch2); | |
@@ -4385,6 +4387,7 @@ void MacroAssembler::I8x16Shuffle(Simd128Register dst, Simd128Register src1, | |||
| 4385 | 4387 | Simd128Register src2, uint64_t high, | |
| 4386 | 4388 | uint64_t low, Register scratch1, | |
| 4387 | 4389 | Register scratch2, Simd128Register scratch3) { | |
| 4390 | + DCHECK(scratch2 != r0); | ||
| 4388 | 4391 | mov(scratch1, Operand(low)); | |
| 4389 | 4392 | mov(scratch2, Operand(high)); | |
| 4390 | 4393 | mtvsrdd(scratch3, scratch2, scratch1); | |
@@ -4673,6 +4676,7 @@ void MacroAssembler::S128Not(Simd128Register dst, Simd128Register src) { | |||
| 4673 | 4676 | ||
| 4674 | 4677 | void MacroAssembler::S128Const(Simd128Register dst, uint64_t high, uint64_t low, | |
| 4675 | 4678 | Register scratch1, Register scratch2) { | |
| 4679 | + DCHECK(scratch2 != r0); | ||
| 4676 | 4680 | mov(scratch1, Operand(low)); | |
| 4677 | 4681 | mov(scratch2, Operand(high)); | |
| 4678 | 4682 | mtvsrdd(dst, scratch2, scratch1); | |
| Original file line number | Diff line number | Diff line change | |
|---|---|---|---|
@@ -2743,7 +2743,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( | |||
| 2743 | 2743 | break; | |
| 2744 | 2744 | } | |
| 2745 | 2745 | case kPPC_I8x16BitMask: { | |
| 2746 | - __ I8x16BitMask(i.OutputRegister(), i.InputSimd128Register(0), r0, ip, | ||
| 2746 | + __ I8x16BitMask(i.OutputRegister(), i.InputSimd128Register(0), ip, r0, | ||
| 2747 | 2747 | kScratchSimd128Reg); | |
| 2748 | 2748 | break; | |
| 2749 | 2749 | } | |
| Original file line number | Diff line number | Diff line change | |
|---|---|---|---|
@@ -2861,7 +2861,7 @@ void LiftoffAssembler::emit_v128_anytrue(LiftoffRegister dst, | |||
| 2861 | 2861 | ||
| 2862 | 2862 | void LiftoffAssembler::emit_i8x16_bitmask(LiftoffRegister dst, | |
| 2863 | 2863 | LiftoffRegister src) { | |
| 2864 | - I8x16BitMask(dst.gp(), src.fp().toSimd(), r0, ip, kScratchSimd128Reg); | ||
| 2864 | + I8x16BitMask(dst.gp(), src.fp().toSimd(), ip, r0, kScratchSimd128Reg); | ||
| 2865 | 2865 | } | |
| 2866 | 2866 | ||
| 2867 | 2867 | void LiftoffAssembler::emit_s128_const(LiftoffRegister dst, | |
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