PIC microcontrollers

/pɪk/) is a family of microcontrollers made by Microchip Technology, derived from the PIC1640 originally developed by General Instrument's Microelectronics Division. The name PIC initially referred to Peripheral Interface Controller, and was subsequently expanded for a short time to include Programmable Intelligent Computer, though the name PIC is no longer used as an acronym for any term. The first parts of the family were available in 1976; by 2013 the company had shipped more than twelve billion individual parts, used in a wide variety of embedded systems.

The PIC was originally designed as a peripheral for the General Instrument CP1600, the first commercially available single-chip 16-bit microprocessor. To limit the number of pins required, the CP1600 had a complex highly-multiplexed bus which was difficult to interface with, so in addition to a variety of special-purpose peripherals, General Instrument made the programmable PIC1640 as an all-purpose peripheral. With its own small RAM, ROM and a simple CPU for controlling the transfers, it could connect the CP1600 bus to virtually any existing 8-bit peripheral. While this offered considerable power, GI's marketing was limited and the CP1600 was not a success. However, GI had also made the PIC1650, a standalone PIC1640 with additional general-purpose I/O in place of the CP1600 interface. When the company spun off their chip division to form Microchip in 1985, sales of the CP1600 were all but dead, but the PIC1650 and successors had formed a major market of their own, and they became one of the new company's primary products.

Early models only had mask ROM for code storage, but with its spinoff it was soon upgraded to use EPROM and then EEPROM, which made it possible for end-users to program the devices in their own facilities. All current models use flash memory for program storage, and newer models allow the PIC to reprogram itself. Since then the line has seen significant change; memory is now available in 8-bit, 16-bit, and, in latest models, 32-bit wide. Program instructions vary in bit-count by family of PIC, and may be 12, 14, 16, or 24 bits long. The instruction set also varies by model, with more powerful chips adding instructions for digital signal processing functions. The hardware implementations of PIC devices range from 6-pin SMD, 8-pin DIP chips up to 144-pin SMD chips, with discrete I/O pins, ADC and DAC modules, and communications ports such as UART, I2C, CAN, and even USB. Low-power and high-speed variations exist for many types.

The manufacturer supplies computer software for development known as MPLAB X, assemblers and C/C++ compilers, and programmer/debugger hardware under the MPLAB and PICKit series. Third party and some open-source tools are also available. Some parts have in-circuit programming capability; low-cost development programmers are available as well as high-volume production programmers.

PIC devices are popular with both industrial developers and hobbyists due to their low cost, wide availability, large user base, an extensive collection of application notes, availability of low cost or free development tools, serial programming, and re-programmable flash-memory capability.

Microchip PIC16C58A PIC16LF870 in SOIC Socket

These devices feature a 14-bit wide code memory, and an improved 8-level (16-level on recent variants) deep call stack. The instruction set differs very little from the baseline devices, but the two additional opcode bits allow 128 registers and 2048 words of code to be directly addressed. There are a few additional miscellaneous instructions, and two additional 8-bit literal instructions, add and subtract. The mid-range core is available in the majority of devices labeled PIC12 and PIC16.

The first 32 bytes of the register space are allocated to special-purpose registers; the remaining 96 bytes are used for general-purpose RAM. If banked RAM is used, the high 16 registers (0x70–0x7F) are global, as are a few of the most important special-purpose registers, including the STATUS register, which holds the RAM bank select bits. (The other global registers are FSR and INDF, the low 8 bits of the program counter PCL, the PC high preload register PCLATH, and the master interrupt control register INTCON.)

The PCLATH register supplies high-order instruction address bits when the 8 bits supplied by a write to the PCL register, or the 11 bits supplied by a GOTO or CALL instruction, are not sufficient to address the available ROM space.

The PIC17 series never became popular and has been superseded by the PIC18 architecture (however, see clones below). The PIC17 series is not recommended for new designs, and availability may be limited to users.

Improvements over earlier cores are 16-bit wide opcodes (allowing many new instructions), and a 16-level deep call stack. PIC17 devices were produced in packages from 40 to 68 pins.

The PIC17 series introduced a number of important new features:

• a memory mapped accumulator
• read access to code memory (table reads)
• direct register-to-register moves (prior cores needed to move registers through the accumulator)
• an external program memory interface to expand the code space
• an 8-bit × 8-bit hardware multiplier
• a second indirect register pair
• auto-increment/auto-decrement addressing controlled by control bits in a status register (ALUSTA)

A significant limitation was that RAM space was limited to 256 bytes (26 bytes of special function registers, and 232 bytes of general-purpose RAM), with awkward bank-switching in the models that supported more.

MIPS @ 80 MHz)

The largest flash memory: 512 kB

One instruction per clock cycle execution

The first cached processor

Allows execution from RAM

Full Speed Host/Dual Role and OTG USB capabilities

Full JTAG and 2-wire programming and debugging

Real-time trace

In November 2013, Microchip introduced the PIC32MZ series of microcontrollers, based on the MIPS M14K core. The PIC32MZ series include:

• 252 MHz core speed, 415 DMIPS
• Up to 2 MB Flash and 512 KB RAM
• New peripherals including high-speed USB, crypto engine and SQI

In 2015, Microchip released the PIC32MZ EF family, using the updated MIPS M5150 Warrior M-class processor.

In 2017, Microchip introduced the PIC32MZ DA Family, featuring an integrated graphics controller, graphics processor and 32MB of DDR2 DRAM.

In June 2016, Microchip introduced the PIC32MM family, specialized for low-power and low-cost applications. The PIC32MM features core-independent peripherals, sleep modes down to 500 nA, and 4 x 4 mm packages. The PIC32MM microcontrollers use the MIPS Technologies M4K, a 32-bit MIPS32 processor. They are meant for very low power consumption and limited to 25 MHz. Their key advantage is to support the 16-bit instructions of MIPS, making program size much more compact (about 40%)

Microchip introduced the PIC32MK family in 2017, specialized for motor control, industrial control, Industrial Internet of Things (IIoT) and multi-channel CAN applications.

Microchip's PIC32C products also use the PIC trademark, but similarly have a completely different architecture. PIC32C products employ the Arm processor architecture, including various lines using Cortex-M0+, M4, M7, M23, and M33 cores. They are offered in addition to the Arm-based SAM series of MCUs which Microchip inherited from its acquisition of Atmel.

Microchip's PIC64 products use the PIC trademark, but have a completely different architecture, and are described here only briefly.

In July 2024, Microchip introduced the PIC64 series of high-performance multi-core microprocessors. The series will initially use the RISC-V instruction set, however Microchip is also planning versions with ARM Cortex-A cores. The PIC64 series will include the PIC64GX line, which focuses on intelligent edge applications, and the PIC64-HPSC line, which is radiation-hardened and focuses on spaceflight applications.

The PIC architecture (excluding the unrelated PIC32 and PIC64) is a one-operand accumulator machine like the PDP-8 or the Apollo Guidance Computer. Its characteristics are:

• One accumulator (W0), which is an implied operand of almost every instruction.
• A small number of fixed-length instructions, with mostly fixed timing (2 clock cycles, or 4 clock cycles in 8-bit models).
• A small amount of addressable data space (32, 128, or 256 bytes, depending on the family), extended through banking
• Separate code and data spaces (Harvard architecture).
• Instruction memory is wider than data memory, allowing immediate constants within an instruction. (This is a major difference from the other early accumulator machines mentioned above.)
• The second operand is a memory location or an immediate constant.
• There are no other addressing modes, although an indirect address mode can be emulated using the indirect register(s).
• Data-space mapped CPU, port, and peripheral registers
  • ALU status flags are mapped into the data space
  • The program counter is also mapped into the data space and writeable (this is used to implement indirect jumps).
• A hardware stack for storing return addresses
• There are only unconditional branch instructions
• Conditional execution is achieved via conditional skip instructions, which conditionally nullify the following instruction.

There is no distinction between memory space and register space because the RAM serves the job of both memory and registers, and the RAM is usually just referred to as "the register file" or simply as "the registers".

PICs have a set of registers that function as general-purpose RAM. Special-purpose control registers for on-chip hardware resources are also mapped into the data space. The addressability of memory varies depending on device series, and all PIC device types have some banking mechanism to extend addressing to additional memory (but some device models have only one bank implemented). Later series of devices feature move instructions, which can cover the whole addressable space, independent of the selected bank. In earlier devices, any register move must be achieved through the accumulator.

To implement indirect addressing, a "file select register" (FSR) and "indirect register" (INDF) are used. A register number is written to the FSR, after which reads from or writes to INDF will actually be from or to the register pointed to by FSR. Later devices extended this concept with post- and pre- increment/decrement for greater efficiency in accessing sequentially stored data. This also allows FSR to be treated almost like a stack pointer (SP).

External data memory is not directly addressable except in some PIC18 devices with high pin count. However, general I/O ports can be used to implement a parallel bus or a serial interface for accessing external memory and other peripherals (using subroutines), with the caveat that such programmed memory access is (of course) much slower than access to the native memory of the PIC MCU.

The code space is generally implemented as on-chip ROM, EPROM or flash ROM. In general, there is no provision for storing code in external memory due to the lack of an external memory interface. The exceptions are PIC17 and select high pin count PIC18 devices.

All PICs handle (and address) data in 8-bit chunks. However, the unit of addressability of the code space is not generally the same as the data space. For example, PICs in the baseline (PIC12) and mid-range (PIC16) families have program memory addressable in the same wordsize as the instruction width, i.e. 12 or 14 bits respectively. In contrast, in the PIC18 series, the program memory is addressed in 8-bit increments (bytes), which differs from the instruction width of 16 bits.

In order to be clear, the program memory capacity is usually stated in number of (single-word) instructions, rather than in bytes.

PICs have a hardware call stack, which is used to save return addresses. The hardware stack is not software-accessible on earlier devices, but this changed with the PIC18 series devices.

Hardware support for a general-purpose parameter stack was lacking in early series, but this greatly improved in the PIC18 series, making the PIC18 series architecture more friendly to high-level language compilers.

and is still among the simplest and cheapest. The Harvard architecture, in which instructions and data come from separate sources, simplifies timing and microcircuit design greatly, and this benefits clock speed, price, and power consumption.

The PIC instruction set is suited to implementation of fast lookup tables in the program space. Such lookups take one instruction and two instruction cycles. Many functions can be modeled in this way. Optimization is facilitated by the relatively large program space of the PIC (e.g. 4096 × 14-bit words on the 16F690) and by the design of the instruction set, which allows embedded constants. For example, a branch instruction's target may be indexed by W, and execute a "RETLW", which does as it is named