Programmable Array Logic

MMI 16R6 in 20-pin DIP AMD 22V10 in 24-pin DIP

Programmable Array Logic (PAL) is a family of programmable logic device semiconductors used to implement logic functions in digital circuits that was introduced by Monolithic Memories, Inc. (MMI) in March 1978. MMI obtained a registered trademark on the term PAL for use in "Programmable Semiconductor Logic Circuits". The trademark is currently held by Lattice Semiconductor.

PAL devices consisted of a small PROM (programmable read-only memory) core and additional output logic used to implement particular desired logic functions with few components.

Using specialized machines, PAL devices were "field-programmable". PALs were available in several variants:

• "One-time programmable" (OTP) devices could not be updated and reused after initial programming. (MMI also offered a similar family called HAL, or "hard array logic", which were like PAL devices except that they were mask-programmed at the factory.)
• UV erasable versions (e.g.: PALCxxxxx e.g.: PALC22V10) had a quartz window over the chip die and could be erased for re-use with an ultraviolet light source just like an EPROM.
• Later versions (PALCExxx e.g.: PALCE22V10) were flash erasable devices.

In most applications, electrically erasable GALs are now deployed as pin-compatible direct replacements for one-time programmable PALs.

PALs were later "second sourced" by Texas Instruments and Advanced Micro Devices.

Early PALs were 20-pin DIP components fabricated in silicon using bipolar transistor technology with one-time programmable (OTP) titanium-tungsten programming fuses. Later devices were manufactured by Cypress, Lattice Semiconductor and Advanced Micro Devices using CMOS technology.

The original 20- and 24-pin PALs were denoted by MMI as medium-scale integration (MSI) devices.

The programmable elements (shown as a fuse) connect both the true and complemented inputs to the AND gates. These AND gates, also known as product terms, are ORed together to form a sum-of-products logic array.

The PAL architecture consists of two main components: a logic plane and output logic macrocells.

The programmable logic plane is a programmable read-only memory (PROM) array that allows the signals present on the device pins, or the logical complements of those signals, to be routed to output logic macrocells.

PAL devices have arrays of transistor cells arranged in a "fixed-OR, programmable-AND" plane used to implement "sum-of-products" binary logic equations for each of the outputs in terms of the inputs and either synchronous or asynchronous feedback from the outputs.

The early 20-pin PALs had 10 inputs and 8 outputs. The outputs were active low and could be registered or combinational. Members of the PAL family were available with various output structures called "output logic macrocells" or OLMCs. Prior to the introduction of the "V" (for "variable") series, the types of OLMCs available in each PAL were fixed at the time of manufacture. (The PAL16L8 had 8 combinational outputs, and the PAL16R8 had 8 registered outputs. The PAL16R6 had 6 registered and 2 combinational outputs, while the PAL16R4 had 4 of each.) Each output could have up to 8 product terms (effectively AND gates); however, the combinational outputs used one of the terms to control a bidirectional output buffer. There were other combinations that had fewer outputs with more product terms per output and were available with active high outputs ("H" series). The "X" series of devices had an XOR gate before the register. There were also similar 24-pin versions of these PALs.

This fixed output structure often frustrated designers attempting to optimize the utility of PAL devices because output structures of different types were often required by their applications. (For example, one could not get 5 registered outputs with 3 active high combinational outputs.) So, in June 1983 AMD introduced the 22V10, a 24-pin device with 10 output logic macrocells. Each macrocell could be configured by the user to be combinational or registered, active high or active low. The number of product terms allocated to an output varied from 8 to 16. This one device could replace all of the 24-pin fixed function PAL devices. Members of the PAL "V" ("variable") series included the PAL16V8, PAL20V8 and PAL22V10.

1. ↑ "Monolithic Memories announces: a revolution in logic design". Electronic Design. 26 (6). Rochelle, NJ: Hayden Publishing: 148B, 148C. March 18, 1978. Introductory advertisement on PAL (Programmable Array Logic).
2. ↑ Monolithic Memories, Inc (MMI) filed for a work mark on the term "PAL" for use in "Programmable Semiconductor Logic Circuits" on April 13, 1978. A registered trademark was granted on April 29, 1980, registration number 1134025. MMI's first use of the term PAL in commerce was on February 21, 1978. The trademark is currently held by Lattice Semiconductor Corporation of Hillsboro, Oregon. Source: United States Patent and Trademark Office online database.
3. ↑ Birkner, John M.; Coli, Vincent J. (1983). PAL Programmable Array Logic Handbook (3rd ed.). Monolithic Memories, Inc.
4. ↑ "CUBEL ChipDesigner 5.0". Logical Devices. August 2013. Archived from the original on May 29, 2015.
5. ↑