Video Coding Engine

Video Code Engine (VCE; earlier referred to as Video Coding Engine, Video Compression Engine or Video Codec Engine in official documentation) is AMD's video encoding application-specific integrated circuit implementing the video codec H.264/MPEG-4 AVC. Since 2012 it was integrated into all of their GPUs and APUs except Oland.

VCE was introduced with the Radeon HD 7000 series on 22 December 2011. VCE occupies a considerable amount of the die surface at the time of its introduction and is not to be confused with AMD's Unified Video Decoder (UVD).

As of AMD Raven Ridge (released January 2018), UVD and VCE were succeeded by Video Core Next (VCN).

N/a AM4 —N/a Basic —N/a FP5 —N/a Fab. (nm) GF 32SHP
(HKMG SOI) GF 28SHP
(HKMG bulk) GF 14LPP
(FinFET bulk) GF 12LP
(FinFET bulk) TSMC N7
(FinFET bulk) TSMC N6
(FinFET bulk) CCD: TSMC N5
(FinFET bulk)
cIOD: TSMC N6
(FinFET bulk) TSMC 4nm
(FinFET bulk) TSMC N40
(bulk) TSMC N28
(HKMG bulk) GF 28SHP
(HKMG bulk) GF 14LPP
(FinFET bulk) GF 12LP
(FinFET bulk) TSMC N6
(FinFET bulk) Die area (mm)228246245245250210156 180210CCD: (2x) 70
cIOD: 122 17875 (+ 28 FCH)107?125149~100 Min TDP (W)351712101565354.543.95106128 Max APU TDP (W)10095654517054182565415 Max stock APU base clock (GHz)33.84.14.13.73.83.63.73.84.03.34.74.31.752.222.23.22.61.23.352.8 Max APUs per node11 Max core dies per CPU1211 Max CCX per core die1211 Max cores per CCX482424 Max CPU cores per APU481682424 Max threads per CPU core1212 Integer pipeline structure3+32+24+24+2+11+3+3+1+21+1+1+12+24+24+2+1 i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHFN/av2v1v2 BMI1, AES-NI, CLMUL, and F16C MOVBE—N/a —N/a MPK, VAES—N/a SGX—N/a — GFNI—N/a AMX——— AMD XDNA—N/a L1 data cache per core (KiB)64163232 L1 data cache associativity (ways)2488 L1 instruction caches per core10.51 10.51 Max APU total L1 instruction cache (KiB)256128192256512256 64128 96 128 L1 instruction cache associativity (ways)2348 2 3 4 8 L2 caches per core10.5110.51 Max APU total L2 cache (MiB)424161212 L2 cache associativity (ways)168168 Max on-die L3 cache per CCX (MiB)—N/a64—N/a64—N/a—N/a Max stock DRAM supportDDR3-1866DDR3-2133DDR3-2133, DDR4-2400DDR4-2400DDR4-2933DDR4-3200, LPDDR4-4266DDR5-4800, LPDDR5-6400DDR5-5200DDR5-5600, LPDDR5x-7500DDR3L-1333DDR3L-1600DDR3L-1866DDR3-1866, DDR4-2400DDR4-2400DDR4-1600DDR4-3200LPDDR5-5500 Max DRAM channels per APU21212 Max stock DRAM bandwidth (GB/s) per APU29.86634.13238.40046.93268.256102.40083.200120.000 10.66612.80014.93319.20038.40012.80051.20088.000 GPU microarchitectureTeraScale 2 (VLIW5)TeraScale 3 (VLIW4)GCN 2nd genGCN 3rd genGCN 5th genRDNA 2RDNA 3TeraScale 2 (VLIW5)GCN 2nd genGCN 3rd genGCN 5th genRDNA 2 GPU instruction setTeraScale instruction setGCN instruction setRDNA instruction setTeraScale instruction setGCN instruction setRDNA instruction set Max stock GPU base clock (MHz)60080084486611081250140021002400400 538600?847900120060013001900 Max stock GPU base GFLOPS480614.4648.1886.71134.517601971.22150.43686.4102.4 86???345.6460.8230.41331.2486.4 3D engineUp to 400:20:8Up to 384:24:6Up to 512:32:8Up to 704:44:16Up to 512:32:8768:48:8128:8:480:8:4128:8:4Up to 192:12:8Up to 192:12:4192:12:4Up to 512:?:?128:?:? IOMMUv1IOMMUv2IOMMUv1?IOMMUv2 Video decoderUVD 3.0UVD 4.2UVD 6.0VCN 1.0VCN 2.1 VCN 2.2VCN 3.1?UVD 3.0UVD 4.0UVD 4.2UVD 6.2VCN 1.0VCN 3.1 Video encoder— N/a FreeSync1
2 1
2 HDCP?1.42.22.3?1.42.22.3 PlayReady——N/a /drm/amdgpu—N/aThe following table shows features of AMD/ATI's GPUs (see also: List of AMD graphics processing units).

Kind 2D 3D Instruction set architecture Not publicly known Multiple TeraScale instruction set GCN instruction set RDNA instruction set Microarchitecture Not publicly known GFX1 GFX2 TeraScale 1
(VLIW5)
(GFX3) TeraScale 2
(VLIW5)
(GFX4) TeraScale 2
(VLIW5)
up to 68xx
(GFX4) TeraScale 3
(VLIW4)
in 69xx
(GFX5) GCN 1st
gen
(GFX6) GCN 2nd
gen
(GFX7) GCN 3rd
gen
(GFX8) GCN 4th
gen
(GFX8) GCN 5th
gen
(GFX9) RDNA
(GFX10.1) RDNA 2
(GFX10.3) RDNA 3
(GFX11) RDNA 4
(GFX12) Type Fixed pipeline Programmable pixel & vertex pipelines Unified shader model Direct3D —N/a 1.1 1.2 1.3 1.5 3.3 4.5 (Windows), 4.6 (Linux Mesa 25.2+) 4.6 Vulkan —N/a N/a VCE 1.0 VCE 2.0 VCE 3.0 or 3.1 VCE 3.4 VCE 4.0 Fluid Motion ? Power saving ? PowerPlay PowerTune PowerTune & ZeroCore Power ? TrueAudio —N/a ? 1.4 2.2 2.3 PlayReady — — Kernel 6.19+

1. ↑ R500 has two instruction sets. Vertex shader cores: "PVS instruction set". Pixel shader cores: "US instruction set".
2. ↑ The Radeon R100 Series has programmable pixel shaders, but do not fully comply with DirectX 8 or Pixel Shader 1.0. See article on R100's pixel shaders.
3. ↑ R300, R400 and R500 based cards do not fully comply with OpenGL 2+ as the hardware does not support all types of non-power of two (NPOT) textures.
4. 1 2 OpenGL 4+ compliance requires supporting FP64 shaders and these are emulated on some TeraScale chips using 32-bit hardware.
5. ↑ Vulkan support is theoretically possible but has not been implemented in a stable driver.
6. ↑ Vulkan support in Linux relies on the AMDgpu kernel driver, the radeon driver does not support Vulkan.
7. 1 2 3 The UVD and VCE were replaced by the Video Core Next (VCN) ASIC in the Raven Ridge APU implementation of Vega.
8. ↑ Video processing for video frame rate interpolation technique. In Windows it works as a DirectShow filter in your player. In Linux, there is no support on the part of drivers and / or community.
9. 1 2 To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
10. ↑ More displays may be supported with native DisplayPort connections, or splitting the maximum resolution between multiple monitors with active converters.
11. 1 2 DRM (Direct Rendering Manager) is a component of the Linux kernel. AMDgpu is the Linux kernel module. Support in this table refers to the most current version.