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[A futuristic scene of a humanoid robot walking through a brightly lit data center corridor, surrounded by glowing servers and digital effects.]
Leading edge, cost-effective process node technologies
Leading edge, cost-effective process node technologies
Leading edge, cost-effective process node technologies
Chiplets and advanced packaging
Chiplets and advanced packaging
Chiplets and advanced packaging
Logic - memory integration
Logic - memory integration
Logic - memory integration
Silicon-proven IPs built with industry-leading partners
Silicon-proven IPs built with industry-leading partners
Silicon-proven IPs built with industry-leading partners
Design enablement
Design enablement
Design enablement
SAFE partner ecosystem
SAFE partner ecosystem
SAFE partner ecosystem
With the onset of the AI era, structural advancements like gate-all-around (GAA) have become imperative to meet power and performance demands. Samsung Foundry was the first foundry to manufacture with the GAA architecture which is optimized for HPC and AI.
With the onset of the AI era, structural advancements like gate-all-around (GAA) have become imperative to meet power and performance demands. Samsung Foundry was the first foundry to manufacture with the GAA architecture which is optimized for HPC and AI.
With the onset of the AI era, structural advancements like gate-all-around (GAA) have become imperative to meet power and performance demands. Samsung Foundry was the first foundry to manufacture with the GAA architecture which is optimized for HPC and AI.
| Technology | Compute / Graphics | Datacenter & Enterprise | |||||
| N/W | AI | Storage | |||||
| Ent | D/C | Training | Inference | Ent | D/C | ||
| Process (recommended) |
5nm, 4nm, 3nm(GAA), 2nm(GAA) |
14nm, 8nm |
5nm, 4nm, 3nm(GAA), 2nm(GAA) |
5nm, 4nm, 3nm(GAA), 2nm(GAA) |
8nm, 5nm, 4nm | 14nm, 8nm, 5nm, 4nm |
|
| Technology | Compute / Graphics | Datacenter & Enterprise | |||||
| N/W | AI | Storage | |||||
| Ent | D/C | Training | Inference | Ent | D/C | ||
| Process (recommended) |
5nm, 4nm, 3nm(GAA), 2nm(GAA) |
14nm, 8nm |
5nm, 4nm, 3nm(GAA), 2nm(GAA) |
5nm, 4nm, 3nm(GAA), 2nm(GAA) |
8nm, 5nm, 4nm | 14nm, 8nm, 5nm, 4nm |
|
Chiplets and advanced packaging are advancing Moore's Law by improving yield and power efficiency. Chiplets come in various types, such as IO, connectivity, and accelerator chiplets, and can be combined to create diverse compute and memory configurations. The architecture is evolving from homogeneous to heterogeneous, supporting D2D connectivity across multiple process nodes, and is being further enhanced by 2.5D and 3D packaging technologies.
Chiplets and advanced packaging are advancing Moore's Law by improving yield and power efficiency. Chiplets come in various types, such as IO, connectivity, and accelerator chiplets, and can be combined to create diverse compute and memory configurations. The architecture is evolving from homogeneous to heterogeneous, supporting D2D connectivity across multiple process nodes, and is being further enhanced by 2.5D and 3D packaging technologies.
Chiplets and advanced packaging are advancing Moore's Law by improving yield and power efficiency. Chiplets come in various types, such as IO, connectivity, and accelerator chiplets, and can be combined to create diverse compute and memory configurations. The architecture is evolving from homogeneous to heterogeneous, supporting D2D connectivity across multiple process nodes, and is being further enhanced by 2.5D and 3D packaging technologies.
Customers can choose one of our flexible business models to procure the package solution
that best meets their chip design:
Customers can choose one of our flexible business models to procure the package solution
that best meets their chip design:
Customers can choose one of our flexible business models to procure the package solution
that best meets their chip design:
Handoff Model: COT (Customer Owned Tooling), COPD (Customer Owned Physical Design)
Handoff Model: COT (Customer Owned Tooling), COPD (Customer Owned Physical Design)
Handoff Model: COT (Customer Owned Tooling), COPD (Customer Owned Physical Design)
Customers can choose from Samsung Foundry packaging offerings or those offered by our performance OSAT partners such as Amkor
Customers can choose from Samsung Foundry packaging offerings or those offered by our performance OSAT partners such as Amkor
Customers can choose from Samsung Foundry packaging offerings or those offered by our performance OSAT partners such as Amkor
Customers can choose one of our flexible business models to procure the package solution that best meets their chip design:
Customers can choose one of our flexible business models to procure the package solution that best meets their chip design:
Customers can choose one of our flexible business models to procure the package solution that best meets their chip design:
2.5D Cube-S: 2.5D Si-Interposer
2.5D Cube-S: 2.5D Si-Interposer
2.5D Cube-S: 2.5D Si-Interposer
2.3D Cube-R
(RDL Interposer)
2.3D Cube-R
(RDL Interposer)
2.3D Cube-R
(RDL Interposer)
2.3D Cube-E: 2.3D RDL-Interposer with Si-Bridge
2.3D Cube-E: 2.3D RDL-Interposer with Si-Bridge
2.3D Cube-E: 2.3D RDL-Interposer with Si-Bridge
3D Cube-T/H: 3D IC
(TCB, HCB)
3D Cube-T/H: 3D IC
(TCB, HCB)
3D Cube-T/H: 3D IC
(TCB, HCB)
2.5D Cube-S brings impressive bandwidth and stunning performance capabilities and is qualified in a wide range of interposer sizes, HBM modules, and package sizes.
Supports Chip-on-Wafer (CoW) technology for developing 2.5D packages with higher HBM module count
2.5D packages with 3.3x silicon interposer, integrating advanced logic and up to eight HBM modules, are fully qualified and available for production
Larger 2.5D packages with expanded silicon interposers are available, supporting more than eight HBM modules and 3,000nF/ or more ISC (Integrated Stack Capacitor)
Silicon interposer wafers are manufactured by Samsung Foundry
2.5D Cube-S brings impressive bandwidth and stunning performance capabilities and is qualified in a wide range of interposer sizes, HBM modules, and package sizes.
Supports Chip-on-Wafer (CoW) technology for developing 2.5D packages with higher HBM module count
2.5D packages with 3.3x silicon interposer, integrating advanced logic and up to eight HBM modules, are fully qualified and available for production
Larger 2.5D packages with expanded silicon interposers are available, supporting more than eight HBM modules and 3,000nF/ or more ISC (Integrated Stack Capacitor)
Silicon interposer wafers are manufactured by Samsung Foundry
2.5D Cube-S brings impressive bandwidth and stunning performance capabilities and is qualified in a wide range of interposer sizes, HBM modules, and package sizes.
Supports Chip-on-Wafer (CoW) technology for developing 2.5D packages with higher HBM module count
2.5D packages with 3.3x silicon interposer, integrating advanced logic and up to eight HBM modules, are fully qualified and available for production
Larger 2.5D packages with expanded silicon interposers are available, supporting more than eight HBM modules and 3,000nF/ or more ISC (Integrated Stack Capacitor)
Silicon interposer wafers are manufactured by Samsung Foundry
Provides a cost-effective alternative to a Si-Bridge solution.
Enables shorter product development and mass production time, through a simplified assembly process flow
Samsung Foundry is developing a 2.3D RDL interposer technology with a line and a space width of 2/2.
Provides a cost-effective alternative to a Si-Bridge solution.
Enables shorter product development and mass production time, through a simplified assembly process flow
Samsung Foundry is developing a 2.3D RDL interposer technology with a line and a space width of 2/2.
Provides a cost-effective alternative to a Si-Bridge solution.
Enables shorter product development and mass production time, through a simplified assembly process flow
Samsung Foundry is developing a 2.3D RDL interposer technology with a line and a space width of 2/2.
2.3D Cube-E gets more cost-effective over a silicon interposer as the size of the interposer becomes much larger but still be able to take the advantage of small L/S from silicon bridges embedded in the RDL interposer based on PLP technology and used as interfaces between silicon dies.
Superior warpage control and power integrity in I-Cube E enables the next generation chiplet architectures possible for many years to come.
A major benefit to an RDL interposer in that it is a low-cost option as a Si-Bridge solution.
RDL interposer provides more design flexibility for less routing interference with fine line width and line spacing. Samsung Foundry is developing a 2.3D RDL interposer technology with a line and space width of 2/2um.
2.3D Cube-E gets more cost-effective over a silicon interposer as the size of the interposer becomes much larger but still be able to take the advantage of small L/S from silicon bridges embedded in the RDL interposer based on PLP technology and used as interfaces between silicon dies.
Superior warpage control and power integrity in I-Cube E enables the next generation chiplet architectures possible for many years to come.
A major benefit to an RDL interposer in that it is a low-cost option as a Si-Bridge solution.
RDL interposer provides more design flexibility for less routing interference with fine line width and line spacing. Samsung Foundry is developing a 2.3D RDL interposer technology with a line and space width of 2/2um.
2.3D Cube-E gets more cost-effective over a silicon interposer as the size of the interposer becomes much larger but still be able to take the advantage of small L/S from silicon bridges embedded in the RDL interposer based on PLP technology and used as interfaces between silicon dies.
Superior warpage control and power integrity in I-Cube E enables the next generation chiplet architectures possible for many years to come.
A major benefit to an RDL interposer in that it is a low-cost option as a Si-Bridge solution.
RDL interposer provides more design flexibility for less routing interference with fine line width and line spacing. Samsung Foundry is developing a 2.3D RDL interposer technology with a line and space width of 2/2um.
Enables higher density, scalability, lower latency, and higher bandwidth tthrough 3D packaging
Proven 3D packaging with high-bandwidth memory (HBM) and CMOS image sensor (CIS)
Ready for mass production using micro-bump CoW and TSV technologies for low-power 3D IC applications
Enables higher density, scalability, lower latency, and higher bandwidth tthrough 3D packaging
Proven 3D packaging with high-bandwidth memory (HBM) and CMOS image sensor (CIS)
Ready for mass production using micro-bump CoW and TSV technologies for low-power 3D IC applications
Enables higher density, scalability, lower latency, and higher bandwidth tthrough 3D packaging
Proven 3D packaging with high-bandwidth memory (HBM) and CMOS image sensor (CIS)
Ready for mass production using micro-bump CoW and TSV technologies for low-power 3D IC applications
Delivers highest transistor density and shortest vertical signal paths
Enables reduced form factor by eliminating bump bonds and other packaging components
Bumpless hybrid Die-to-Wafer (D2W) technology under development
Delivers highest transistor density and shortest vertical signal paths
Enables reduced form factor by eliminating bump bonds and other packaging components
Bumpless hybrid Die-to-Wafer (D2W) technology under development
Delivers highest transistor density and shortest vertical signal paths
Enables reduced form factor by eliminating bump bonds and other packaging components
Bumpless hybrid Die-to-Wafer (D2W) technology under development
Logic memory integration where logic and memory gets optimized. HBM has emerged as a popular memory option for AI training and inference applications. Custom HBM is becoming an attractive option due to its power consumption advantages and customization options.
Logic memory integration where logic and memory gets optimized. HBM has emerged as a popular memory option for AI training and inference applications. Custom HBM is becoming an attractive option due to its power consumption advantages and customization options.
Logic memory integration where logic and memory gets optimized. HBM has emerged as a popular memory option for AI training and inference applications. Custom HBM is becoming an attractive option due to its power consumption advantages and customization options.
Key benefits of using custom HBM:
Improved bandwidth and capacity: By using a die-to-die interface, custom HBM can provide higher bandwidth and capacity while reducing the shoreline.
Reduced power consumption and latency: Integrating the HBM controller into the base die reduces the power consumption and latency associated with traditional HBM solutions.
Increased innovation and flexibility: Custom HBM allows for the integration of additional logic, such as accelerators, memory controllers, or CPUs, into the base die, enabling innovative solutions tailored to specific applications.
Key benefits of using custom HBM:
Improved bandwidth and capacity: By using a die-to-die interface, custom HBM can provide higher bandwidth and capacity while reducing the shoreline.
Reduced power consumption and latency: Integrating the HBM controller into the base die reduces the power consumption and latency associated with traditional HBM solutions.
Increased innovation and flexibility: Custom HBM allows for the integration of additional logic, such as accelerators, memory controllers, or CPUs, into the base die, enabling innovative solutions tailored to specific applications.
Key benefits of using custom HBM:
Improved bandwidth and capacity: By using a die-to-die interface, custom HBM can provide higher bandwidth and capacity while reducing the shoreline.
Reduced power consumption and latency: Integrating the HBM controller into the base die reduces the power consumption and latency associated with traditional HBM solutions.
Increased innovation and flexibility: Custom HBM allows for the integration of additional logic, such as accelerators, memory controllers, or CPUs, into the base die, enabling innovative solutions tailored to specific applications.
PO are modular optical transceivers that can be easily inserted and replaced, providing flexibility and scalability in today's data centers.
CPO allows optical interfaces to be directly integrated with switch ASICs, enabling higher bandwidth density, improved power efficiency,
and enhanced signal integrity. CPO is emerging as a key solution to overcome the limitations of conventional architectures
while supporting more efficient and scalable network designs.
Samsung Foundry offers comprehensive PO and CPO solutions tailored to your needs.
PO are modular optical transceivers that can be easily inserted and replaced, providing flexibility and scalability in today's data centers. CPO allows optical interfaces to be directly integrated with switch ASICs, enabling higher bandwidth density, improved power efficiency, and enhanced signal integrity. CPO is emerging as a key solution to overcome the limitations of conventional architectures while supporting more efficient and scalable network designs.
Samsung Foundry offers comprehensive PO and CPO solutions tailored to your needs.
PO are modular optical transceivers that can be easily inserted and replaced, providing flexibility and scalability in today's data centers. CPO allows optical interfaces to be directly integrated with switch ASICs, enabling higher bandwidth density, improved power efficiency, and enhanced signal integrity. CPO is emerging as a key solution to overcome the limitations of conventional architectures while supporting more efficient and scalable network designs.
Samsung Foundry offers comprehensive PO and CPO solutions tailored to your needs.
1st-Gen PO : a modular pluggable optical solution enabling flexible and scalable connectivity
2nd-Gen PO : next-generation pluggable optic modules featuring a 3D-stacked architecture, optimized for higher bandwidth, improved power efficiency, and high-density integration
CPO Switch : The switch ASIC is integrated with a 3D optical engine(OE) on a shared substrate, minimizing the electrical signal path and reducing power consumption while enabling higher bandwidth density and more efficient optical connectivity
CPO XPU : Co-packaged 3D OE is integrated with the XPU/GPU on interposer, enabling high data throughput, improved power efficiency for AI and high-performance computing applications
1st-Gen PO : a modular pluggable optical solution enabling flexible and scalable connectivity
2nd-Gen PO : next-generation pluggable optic modules featuring a 3D-stacked architecture, optimized for higher bandwidth, improved power efficiency, and high-density integration
CPO Switch : The switch ASIC is integrated with a 3D optical engine(OE) on a shared substrate, minimizing the electrical signal path and reducing power consumption while enabling higher bandwidth density and more efficient optical connectivity
CPO XPU : Co-packaged 3D OE is integrated with the XPU/GPU on interposer, enabling high data throughput, improved power efficiency for AI and high-performance computing applications
1st-Gen PO : a modular pluggable optical solution enabling flexible and scalable connectivity
2nd-Gen PO : next-generation pluggable optic modules featuring a 3D-stacked architecture, optimized for higher bandwidth, improved power efficiency, and high-density integration
CPO Switch : The switch ASIC is integrated with a 3D optical engine(OE) on a shared substrate, minimizing the electrical signal path and reducing power consumption while enabling higher bandwidth density and more efficient optical connectivity
CPO XPU : Co-packaged 3D OE is integrated with the XPU/GPU on interposer, enabling high data throughput, improved power efficiency for AI and high-performance computing applications
| IP | 14nm | 8nm | 5nm | 4nm | 2nm |
| SerDes |  [Shape] |
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| D2D | [Shape] |
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| LPDDR | [Shape] |
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| DDR | [Shape] |
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| GDDR | [Shape] |
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| HBM | [Shape] |
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| Analog IP | [Shape] |
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| IP | 14nm | 8nm | 5nm | 4nm | 2nm |
| SerDes | [Shape] |
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| D2D | [Shape] |
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| PCle | [Shape] |
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| Ethernet | [Shape] |
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| LPDDR | [Shape] |
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| DDR | [Shape] |
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| GDDR | [Shape] |
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| HBM | [Shape] |
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| Analog IP | [Shape] |
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Samsung Foundry design enablement platform encompasses:
Samsung Foundry design enablement platform encompasses:
Samsung Foundry design enablement platform encompasses:
A complete set of PDK files
A complete set of PDK files
A complete set of PDK files
A full suite of libraries and IPs
A full suite of libraries and IPs
A full suite of libraries and IPs
Robust design flow methodologies that are node specific and downloadable for rapid design start
Robust design flow methodologies that are node specific and downloadable for rapid design start
Robust design flow methodologies that are node specific and downloadable for rapid design start
Samsung Foundry works closely with key design enablement and IP partners to optimize the tools and allow for higher design productivity. In addition, our SAFE-QEDA or EDA certification program allows for higher design and silicon success by ensuringthat IP and customer designs meet Samsung Foundry process and packaging technology requirements. Furthermore, our design enablement partners have entered a new era of computational software where the convergence of System Level Design, Artificial Intelligence, and Electronic Design Automation offers enhancements for even greater design optimizations.
All these optimizations provide a robust and reliable design enablement platform which is essential, especially for earlyadoptions of more recent technologies such as Samsung Foundry 5nm EUV,3D IC and soon-to-be available GAA.
Samsung Foundry works closely with key design enablement and IP partners to optimize the tools and allow for higher design productivity. In addition, our SAFE-QEDA or EDA certification program allows for higher design and silicon success by ensuringthat IP and customer designs meet Samsung Foundry process and packaging technology requirements. Furthermore, our design enablement partners have entered a new era of computational software where the convergence of System Level Design, Artificial Intelligence, and Electronic Design Automation offers enhancements for even greater design optimizations.
All these optimizations provide a robust and reliable design enablement platform which is essential, especially for earlyadoptions of more recent technologies such as Samsung Foundry 5nm EUV,3D IC and soon-to-be available GAA.
Samsung Foundry works closely with key design enablement and IP partners to optimize the tools and allow for higher design productivity. In addition, our SAFE-QEDA or EDA certification program allows for higher design and silicon success by ensuringthat IP and customer designs meet Samsung Foundry process and packaging technology requirements. Furthermore, our design enablement partners have entered a new era of computational software where the convergence of System Level Design, Artificial Intelligence, and Electronic Design Automation offers enhancements for even greater design optimizations.
All these optimizations provide a robust and reliable design enablement platform which is essential, especially for earlyadoptions of more recent technologies such as Samsung Foundry 5nm EUV,3D IC and soon-to-be available GAA.
| DK/PDK | Datacenter & Enterprise | ||
| Cadence | Siemens EDA | Synopsys | |
| Timing | [Shape] |
[Shape] |
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| Power | [Shape] |
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| Custom Design | [Shape] |
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| SPICE | [Shape] |
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| P-Cell | [Shape] |
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| DRC/Antenna | [Shape] |
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| Dummy Insertion | [Shape] |
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| LVS | [Shape] |
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| RC Extraction | [Shape] |
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| IR/EM | [Shape] |
[Shape] |
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| DFM | [Shape] |
[Shape] |
[Shape] |
| Package Co-Design | [Shape] |
[Shape] |
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| 2.5/3D | [Shape] |
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| Thermal/Mechanical | [Shape] |
[Shape] |
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| DK/PDK | Datacenter & Enterprise | ||
| Cadence | Siemens EDA | Synopsys | |
| Timing | [Shape] |
[Shape] |
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| Power | [Shape] |
[Shape] |
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| Custom Design | [Shape] |
[Shape] |
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| SPICE | [Shape] |
[Shape] |
[Shape] |
| P-Cell | [Shape] |
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| DRC/Antenna | [Shape] |
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| Dummy Insertion | [Shape] |
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| LVS | [Shape] |
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| RC Extraction | [Shape] |
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| DFM | [Shape] |
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| 2.5/3D | [Shape] |
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A broad ecosystem of services with our SAFE partners includes:
A broad ecosystem of services with our SAFE partners includes:
A broad ecosystem of services with our SAFE partners includes:
Best-in-class reference flows from major electronic design automation (EDA) vendors.
Best-in-class reference flows from major electronic design automation (EDA) vendors.
Best-in-class reference flows from major electronic design automation (EDA) vendors.
Comprehensive libraries of standard cells, memory compilers, and I/O interfaces.
Comprehensive libraries of standard cells, memory compilers, and I/O interfaces.
Comprehensive libraries of standard cells, memory compilers, and I/O interfaces.
An extensive IP portfolio including mixed-signal, peripheral, multimedia cores, and interfaces.
An extensive IP portfolio including mixed-signal, peripheral, multimedia cores, and interfaces.
An extensive IP portfolio including mixed-signal, peripheral, multimedia cores, and interfaces.
Predictive design-for-manufacturing solutions to address yield upstream in the design flow.
Predictive design-for-manufacturing solutions to address yield upstream in the design flow.
Predictive design-for-manufacturing solutions to address yield upstream in the design flow.
Advanced packaging and testing.
Advanced packaging and testing.
Advanced packaging and testing.
Design Service Partners
Design Service Partners
Design Service Partners
Cloud design support
Cloud design support
Cloud design support
OSATS
OSATS
OSATS
Samsung Foundry is a trusted partner for customers designing cutting-edge, performance-intensive solutions. We deliver robust, reliable, and innovative technologies that integrate seamlessly to produce next-generation AI SoCs and advanced chiplet platforms. By leveraging our expertise and technology, customers can create innovative solutions that drive their success.
Discover how Samsung Foundry can help you achieve your goals.
Contact Us to explore how we can support your business.
Samsung Foundry is a trusted partner for customers designing cutting-edge, performance-intensive solutions. We deliver robust, reliable, and innovative technologies that integrate seamlessly to produce next-generation AI SoCs and advanced chiplet platforms. By leveraging our expertise and technology, customers can create innovative solutions that drive their success.
Discover how Samsung Foundry can help you achieve your goals.
Contact Us to explore how we can support your business.
Samsung Foundry is a trusted partner for customers designing cutting-edge, performance-intensive solutions. We deliver robust, reliable, and innovative technologies that integrate seamlessly to produce next-generation AI SoCs and advanced chiplet platforms. By leveraging our expertise and technology, customers can create innovative solutions that drive their success.
Discover how Samsung Foundry can help you achieve your goals.
Contact Us to explore how we can support your business.
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