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ECE Undergraduate @ NIT Warangal
Low-level thinker. Hardware-first mindset. Architecture obsessed
🟥🟧🟨🟩🟦🟪⬛⬜
🧩 Engineering sophomore obsessed with how things actually work
🔩 I operate close to silicon and system level, timing paths and architectural bottlenecks
- Branch prediction internals
- Cache behavior and replacement logic
- Pipeline-level reasoning
- Performance vs hardware cost tradeoffs
- ML models constrained by latency and area
- Online learning on real hardware
- Accuracy is useless without feasibility
- RTL design (Verilog)
- Timing-aware design decisions
- Sensor → hardware → inference pipelines
- Prototyping ideas that don’t hide behind simulators
🟦 Computer Architecture
🟦 Verilog
🟦 FPGA Architecture
🟦 Timing & Resource Analysis
🟨 C / C++
🟨 Python (modeling & validation)
🟨 MATLAB
🟨 Linux
🟨 Git
⚡ Deepening architecture-level ML understanding
⚡ Translating research ideas into RTL
⚡ Long-term: systems research
🔴🟠🟡🟢🔵🟣⚫⚪
Popular repositories Loading
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Computer-Architecture-Project-SPARC Computer-Architecture-Project-SPARC Public
Forked from FrenzyExists/Computer-Architecture-Project-SPARC
Final Project of the Computer Architecture (ICOM4215) course, Spring 2023. The project documents the journey of three students learning the basics of the vast world of FPGAs and hardware design in …
Verilog 1
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Perceptron-Based-Dynamic-Branch-Prediction Perceptron-Based-Dynamic-Branch-Prediction Public
Perceptron-Based Dynamic Branch Prediction with Trace-Driven Evaluation (Self-Project)
Verilog 1
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Verilog-Projects Verilog-Projects Public
Forked from nxbyte/Verilog-Projects
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
Verilog
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