Popular repositories Loading

1. RISCV-RV32IM-CPU RISCV-RV32IM-CPU Public

   Verilog implementation of a 5-stage pipelined RISC-V RV32IM CPU featuring Dynamic Branch Prediction, Caches, and Hardware Multiplication/Division

   Verilog 2

2. UART-IP-CORE UART-IP-CORE Public

   A configurable, full-duplex UART IP Core in Verilog featuring AXI4-Lite interface and Asynchronous FIFOs for robust SoC integration.

   Verilog 1

3. MIPS-Processor MIPS-Processor Public

   5-stage pipelined 32-bit MIPS microprocessor and cache in Verilog

   Verilog 1 1

4. CHI_Interconnect CHI_Interconnect Public

   Verilog 1

5. HCMUT-LAB-DSA HCMUT-LAB-DSA Public

   C++

6. MCU-LAB1 MCU-LAB1 Public

   LAB1-MCU-2025