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Forked from The-OpenROAD-Project/OpenDB
Database and Tool Framework for EDA
C++ 1
Forked from tomverbeure/yosys_gatemap
An example that shows how to map a design to a custom cell library.
Verilog
Forked from tomverbeure/yosys_split_ops
Yosys techmaps to split operations on large vectors into multiple smaller ones.
Verilog
Forked from tomverbeure/yosys_techmap_blog
Example repo for blog post
Verilog
A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.
Design circuit boards with code! ✨ Get software-like design reuse 🚀, validation, version control and collaboration in hardware; starting with electronics ⚡️
Multi-platform nightly builds of open source digital design and verification tools
Structural Netlist API (and more) for EDA post synthesis flow development
PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g., Verilog, SystemVerilog)
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