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Report abusePostdoctoral researcher at the University of Passau, Germany, working on hardware security and low-level systems. My current work focuses on implementing and evaluating cybersecurity mechanisms as part of the CipherCell project.
My primary interests focus on low-level systems and hardware security:
Full Stack framework to analyze PUFs on commercially available non-volatile memories
Designed and implemented a full-stack PUF evaluation platform consisting of custom PCBs and a ZCU102 MPSoC, including a Verilog-based memory controller and PUF scheduler. The FPGA interfaces via AXI with custom PS firmware providing networking functionality and is complemented by a GUI for experiment scheduling and monitoring[1].
Accelerating and Securiting DDS Communication using MPSocs
Implementation of a hardware architecture on Xilinx UltraScale+ for dynamic priority scheduling of Ethernet packets forwarded to multiple CPUs on an MPSoC. The pipeline includes a Verilog implementation of the SipHash message authentication algorithm for packet integrity verification. Authentication keys are derived from a ring oscillator PUF specifically tuned to the physical characteristics of the UltraScale+ fabric, eliminating the need for external key storage.[2]
Characterization of Carbon Nanotube FETs and Memristors Experimental setup for high-precision electrical characterization of Carbon Nanotube FETs and memristors. The core challenge lies in resolving the extremely low currents exhibited by CNT-FETs, which demands careful PCB design and signal routing. The hardware side comprises a custom switch matrix[3] built on a self-designed PCB, enabling flexible, low-noise charactierization. On the software side, an automated platform handles experiment scheduling, execution, and result evaluation, reducing manual intervention and ensuring reproducible measurements.
Mountain biking and hiking in the Bavarian Alps, skiing in winter, landscape photography on travels. I hold a private pilot license and volunteer with my local fire department.
A comprehensive test platform for advanced memory device characterization combining FPGA acceleration, real-time firmware, and automated experiment scheduling
Jupyter Notebook
A guide on how to Setup Petalinux on a ZCU102 while flashing a standalone application on the Cortex R5.
Framework to control Oscilloscopes, SMUs, Function Generators and DC Powersupplies via Ethernet.
This repository contains source code and PCB designs for a switch matrix to measure carbon nanotube field-effect transistors.
C
This repo contains the development of the frontend to execute, filter and analyse PUF-related (Physical Unclonable Function) behavior tests.
JavaScript 1
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