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1. hyperbus_controller hyperbus_controller Public

   Xilinx UltraScale+ based HyperBus controller for HyperRam memories

   VHDL 2

2. SpartanESC SpartanESC Public

   Brushless BLDC Motor Controller based on Spartan UltraScale+ FPGA. Featuring integrated GaN FETs

   1

3. axi_dualport_hb_bridge axi_dualport_hb_bridge Public

   This is a quick solution to support dual HyperRam devices in a Xilinx based FPGA implementation. 64-bit axi slave on one side, then this bridge will stripe the data across the dual 32-bit axi maste…

   SystemVerilog 1

4. uart_telnet_bridge uart_telnet_bridge Public

   Tiny python script to bridge the local uart to network telnet connection. Built intentionally without authentication since telnet authentication is not secure. Intended for use in a lab or private …

   Python 1

5. e_uart e_uart Public

   A uart with deep FIFOs, interrupt coalescing and support for 32-bit reads and writes.

   VHDL

6. servo_pwm servo_pwm Public

   Pulse generator optimized for RC Servo Control

   Verilog