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Need regs_template.txt to modify module registers.
Status: Open.
#9
In NetFPGA/NetFPGA-PLUS;
·
PaperL
opened
on Oct 30, 2023
Help wanted with NetFPGA-PLUS Reference Switch
Status: Open.
#6
In NetFPGA/NetFPGA-PLUS;
·
lukaszkwiatkowskii
opened
on Jul 3, 2023
Why is tready signal from output_queues.v is set to always 1?
Status: Open.
#4
In NetFPGA/NetFPGA-PLUS;
·
Horacehxw
opened
on Sep 26, 2022
Bug in axis_sim_stim.vhd file
Status: Open.
#3
In NetFPGA/NetFPGA-PLUS;
·
Vic0428
opened
on Jan 17, 2022
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