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NikosDelijohn (Nick) · GitHub

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  1. Tethorax Tethorax Public

    RISC V 32 bit Base ISA Implementation.

    VHDL 15 2

  2. CS-polito CS-polito Public archive

    Solutions for the laboratory sessions of the first year undergraduate course "Computer Sciences" @ Politecnico di Torino

    Python 34 19

  3. cad-polito-it/testcrush cad-polito-it/testcrush Public

    A Software Test Library compaction tool based on VC-Z01X.

    Python 2 2

  4. cad-polito-it/r4ves cad-polito-it/r4ves Public

    RiscV Environment for Simulation (R4VES) is a generic and modular framework that eases the grunt work required in order to perform pre/post-synthesis logic and fault simulation on RISC-V cores base…

    Verilog 1 1

  5. finjenv finjenv Public

    Fault injection environment (finjenv) of permanent hardware faults for various arithmetic circuits based on QuestaSIM logic simulator

    Verilog 1

  6. ksa ksa Public

    A synthesizable and modular Kogge-Stone Adder (KSA) implementation in SystemVerilog.

    SystemVerilog 3

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