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Report abuseI'm an Aspiring Automation Engineer with a passion for the hardware-software interface, Robotics, Homelabbing, RISC-V architecture, FPGA design. I am currently a Dual Degree student at the University of Bologna and Tongji University, Shanghai.
🔭 I’m currently working on:
🌱 I’m currently learning:
📫 How to reach me:
⚡ My Key Projects:
An optimized autonomous frontier-based exploration and mapping package for ROS 2 and Nav2
Python
A custom graphics peripheral in Verilog for a RISC-V SoC, featuring an ICB bus interface and controlled by C firmware to render ASCII text on an HDMI display.
Verilog 2
A 5-stage pipelined processor compliant with the RISC-V RV32I ISA, featuring full hazard detection and resolution.
SystemVerilog 1
An FSM-controlled automotive tail light system in Verilog for a Xilinx Artix-7 FPGA, featuring a unique emergency mode with a real-time 7-segment display timer.
Verilog 1
A high-efficiency home server build based on OpenMediaVault 7, optimized for 2009-era legacy hardware with limited resources
Shell
My first linux rice, created for Cinnamon DE (used Mint as OS)
CSS 14
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