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AutoHDW · GitHub

AutoHDW

Toward Hardware Design Automation

AutoHDW

Toward hardware design automation. A research team of Southeast University.

Publications

  1. Y. Mao et al., FLAG: Formula-LLM-Based Auto-Generator for Baseband Hardware, IEEE International Symposium on Circuits and Systems (ISCAS), 2024. [IEEE Xplore] [DOI]
  2. W. Zhao et al., Flexible High-Level Synthesis Library for Linear Transformations, IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), 2024. [IEEE Xplore] [PDF] [DOI] [GitHub] [Website]
  3. W. Zhao et al., Automatic Timing-Driven Top-Level Hardware Design for Digital Signal Processing, IEEE International Conference on ASIC (ASICON), 2023. [IEEE Xplore] [PDF] [DOI]

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    Python Templated Verilog

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  4. ahdw-vscode ahdw-vscode Public

    VS Code Extension for AHDW Language

    TypeScript 3

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