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Report abuseKeccak/SHA-3 family IP core in SystemVerilog. FIPS-202 + Ethereum Keccak-256 compliant, dual-licensed.
SystemVerilog 2
SPI master+slave IP core in SystemVerilog. All 4 modes (CPOL/CPHA), parametrizable bit-width, FIFO, optional AXI4-Lite wrapper.
SystemVerilog 2
AES-128 IP core in SystemVerilog. FIPS-197 compliant, dual-licensed, with secure (DPA-resistant) and pipelined variants.
C++ 1
Open-source JTAG and SWD pinout discoverer for STM32G431RB Nucleo. Bare-metal C in 5.9 KB, 70 integration tests. JTAGulator-style brute-force IDCODE / DPIDR scan.
Python 1
AES-256 FPGA IP core in SystemVerilog. FIPS-197 compliant, NIST-validated, dual-licensed.
C++
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