Add the runtime EVEX map-4 prefix builder (ND/NF/EGPR bits per APX
spec rev 8, Fig. 3.3), wire it into the meta code generator, and enable
the NDD `addq` instruction. Verified with a byte-exact encoding test
(62 F4 F4 18 01 C2).

Instruction selection (ISLE lowering) and EGPR register allocation are
not part of this change; the `.clif` filetest cannot select these
instructions yet.

Add a `use_apx` ISLE predicate and lower 64-bit `iadd` to the NDD form of
`addq` (EVEX map 4) when the `has_apx` target flag is enabled. Gate the
instruction on the `apx` assembler feature and align the NDD destination
with the EVEX `vvvv` operand so the result is written to a fresh register
without clobbering either input. Add filetests exercising the new lowering
and the `has_apx` flag parsing.