A modular build system for hardware ("make for silicon"). The project philosophy is to "make the complex possible while keeping the simple simple".

The project foundation is a standardized dynamic JSON schema for configuring and tracking of compile time parameter related to design setup, libraries, tools, Process Design Kits (PDKs), flows, constraints, compiler time options, and run time metrics, Advanced projects (like ASICs) are far too complex be handled manually through markup languages like JSON/YAML, so the project also includes a simple (but powerful) object oriented Python API for compilation setup, run time scheduling, and results analysis. For more information about the project motivation and design philosophy, you can refer to the following paper.

A. Olofsson, W. Ransohoff, N. Moroze, "Invited: A Distributed Approach to Silicon Compilation", 59th Design Automation Conference (DAC), 10-14 July 2022, San Francisco, CA, USA. Published, 7/2022.

• Ease-of-use: Programmable with a simple Python API
• Portability: Powerful dynamic JSON schema supports ASIC and FPGA design and simulation
• Speed: Flowgraph compilation model enables cloud scale execution.
• Friction-less: Remote execution model enables "zero install" compilationm
• Modularity: Tool abstraction layer makes it easy to add/port new tools to the project.
• Provenance: Comilation manifests created automatically during execution.
• Documentated: An extensive set of auto-generated high quality reference documents.
• In-use: Actively used by Zero ASIC for commercial tapeouts at advanced process node.

SiliconCompiler is available as wheel packages on PyPI for macOS, Windows and Linux platforms. For working Python 3.6-3.10 environment, just use pip.

python -m pip upgrade siliconcompiler

Converting RTL into DRC clean GDS takes less than 10 lines of simple Python code.

import siliconcompiler                      # import python package
chip = siliconcompiler.Chip('heartbeat')    # create chip object
chip.load_target('freepdk45_demo')          # load a pre-defined target
chip.set('input', 'verilog', 'heartbeat.v') # set input sources
chip.set('input', 'sdc', 'heartbeat.sdc')   # set constraints
#chip.set('option','remote', True)          # enable remote execution
chip.run()                                  # run compilation
chip.summary()                              # print summary
chip.show()                                 # show layout

To reduce the pain of tool installation, the project supports free remote compilation at siliconcompiler.com.

1. Sign up for a free beta account,
2. Create a credentials file
3. Set the remote option to True (see example above)
4. Run

Simple designs can be compiled using the built in command line 'sc' app:

sc -remote -input "verilog heartbeat.v" -design heartbeat -target "freepdk45_demo"

The full reference manual and tutorials can be found HERE.

Complete installation instructions are available in the Installation Guide.

To install the project from source (recommended for developers only).

git clone https://github.com/siliconcompiler/siliconcompiler
cd siliconcompiler
git submodule update --init --recursive third_party/tools/openroad
pip install -r requirements.txt
python -m pip install -e .

Installation instructions for all external tools can be found in the Tools section of the reference manual. We have included shell setup scripts (Ubuntu) for most of the supported tools. See the ./setup directory for a complete set of scripts.

SiliconCompiler is an open-source project and welcomes contributions. To find out how to contribute to the project, see our Contributing Guidelines.

We use GitHub Issues for tracking requests and bugs.

Apache License 2.0