Interchange formats for chip design.

Vlsir defines data schema for integrated circuit (IC) circuits, layouts, and simulations, using Google's Protocol Buffer schema definition language.

The name Vlsir is a merger of VLSI (very large scale integration - a way-outdated chip-world acronym) and IR (intermediate representation - the term every cool-kid copying compiler designers uses nowadays).

All of Vlsir's schema-definitions live in the protos directory.

Vlsir defines a data schema, which related projects use in code. Projects using vlsir can be written in any language with protobuf-compiler bindings - which includes essentially every popular programming language. Existing projects have prominently used Python, C++, and Rust. In this repository we have supported bindings for Python and Rust which can be found in bindings and downloaded from their respective package managers:

The Vlsir repository also serves as home for the Python-language VlsirTools package. VlsirTools is a collection of tools for working with Vlsir's schema, including:

• Netlisting to industry-standard formats (SPICE, Verilog, etc.)
• Drivers and result-parsers for Spice-class simulators

The repository includes build scripts for Python, Rust, C++, Javascript and Julia bindings, of which only Rust and Python are actively maintained and tested. These can all be built individually with scripts/build_<your-language-here>.sh or with either of the two joint scripts:

• build_supported.sh, this builds all supported bindings for use by Vlsir developers
• build_all_recipes.sh, this builds all bindings and is primarily used for testing

To build, run the script below:

git clone git@github.com:Vlsir/Vlsir
cd Vlsir
scripts/build_<build_flavour>.sh

Ongoing, co-developed projects which use vlsir: