chipfoundry/openframe_user_project · GitHub

• Overview
• Documentation & Resources
• Prerequisites
• Project Structure
• Starting Your Project
• Development Flow
• Local Precheck
• Checklist for Shuttle Submission

OpenFrame is a ChipFoundry project template that provides only a bare padframe (no integrated SoC), giving you a 15 mm² user area and 44 GPIOs to design your own custom chip. You are free to implement your design and directly connect it to the available GPIOs throught the pins provided on the openframe wrapper.

For detailed hardware specifications and design guidelines, refer to the following official documents:

• ChipFoundry Marketplace: Access additional IP blocks, EDA tools, and shuttle services.

Ensure your environment meets the following requirements:

1. Docker Linux | Windows | Mac
2. Python 3.8+ with pip.
3. Git: For repository management.

A successful OpenFrame project requires a specific directory layout for the automated tools to function:

Create a new repository based on the openframe_user_project template and clone it to your local machine:

git clone <your-github-repo-URL>
pip install chipfoundry-cli
cd <project_name>

cf init

This creates .cf/project.json with project metadata. This must be run before any other commands

Install the ChipFoundry CLI tool and set up the local environment (PDKs, OpenLane, and OpenFrame):

cf setup

The cf setup command installs:

• OpenFrame: The OpenFrame harness template.
• OpenLane: The RTL-to-GDS hardening flow.
• PDK: Skywater 130nm process design kit.
• Timing Scripts: For Static Timing Analysis (STA).

Hardening is the process of synthesizing your RTL and performing Place & Route (P&R) to create a GDSII layout.

Create a subdirectory for each custom macro under openlane/ containing your config.json.

cf harden --list         # List detected configurations
cf harden <macro_name>   # Harden a specific macro

Instantiate your module(s) in verilog/rtl/openframe_project_wrapper.v.

Update openlane/openframe_project_wrapper/config.json environment variables (VERILOG_FILES_BLACKBOX, EXTRA_LEFS, EXTRA_GDS_FILES) to point to your new macros.

Finalize the top-level user project:

cf harden openframe_project_wrapper

Connecting to Power:

• Ensure your design is connected to power using the power pins on the wrapper.
• Use the vccd1_connection and vssd1_connection macros, which contain the necessary vias and nets for power connections.

We use cocotb for functional verification. Ensure your file lists are updated in verilog/includes/.

Run RTL Simulation:

cf verify <test_name>

Run Gate-Level (GL) Simulation:

cf verify <test_name> --sim gl

Run all tests:

cf verify --all

Before submitting your design for fabrication, run the local precheck to ensure it complies with all shuttle requirements:

cf precheck

You can also run specific checks or disable LVS:

cf precheck --disable-lvs                    # Skip LVS check
cf precheck --checks license --checks makefile  # Run specific checks only

• Top-level macro is named openframe_project_wrapper.
• Full Chip Simulation passes for both RTL and GL.
• Hardened Macros are LVS and DRC clean.
• openframe_project_wrapper matches the required pin order/template.
• Design is properly connected to power (vccd1/vssd1).
• Design passes the local cf precheck.
• Documentation (this README) is updated with project-specific details.