Issues

• Subfield domain association to wires should be rejected

  chipsalliance/chisel#5507 · opened on Oct 5, 2026

• [Feature Request] Scalatest Cli support for FST waveform

  chipsalliance/chisel#5504 · opened on Oct 4, 2026

• Using chisel3.*Param/ExtModule emits chisel3.experimental deprecation warnings on Scala 3

  chipsalliance/chisel#5499 · opened on Sep 27, 2026

• Naming Plugin and Object Pattern

  Bug

  chipsalliance/chisel#5430 · opened on Jul 1, 2026
  2

• MultiClockSpec chiselTest fails with recent Verilator version

  chipsalliance/chisel#5418 · opened on Jun 16, 2026
  3

• [firrtl] Hardware with nested direction generates failing firrtl with Reg / RegNext

  chipsalliance/chisel#5411 · opened on Jun 14, 2026
  4

• Better error message for misuse of Domain association to ports

  chipsalliance/chisel#5407 · opened on Jun 9, 2026
  1

• ModuleChoice does not connect implicit clock/reset to FixedIOModule targets

  chipsalliance/chisel#5383 · opened on May 27, 2026

• "-disable-all-randomization" can't work when the module with RequireAsyncReset

  chipsalliance/chisel#5357 · opened on May 18, 2026

• [ChiselSim] Flag --trace-threads is deprecated since Verilator v5.048

  chipsalliance/chisel#5335 · opened on May 14, 2026
  3

• [doc] Add documentation about layer-under-layer errors and how to mitigate

  chipsalliance/chisel#5244 · opened on Mar 25, 2026

• suffix always be "sv"

  chipsalliance/chisel#5231 · opened on Mar 14, 2026
  1

• ChiselSim cannot deal with 0-width signals and DontCare values

  chipsalliance/chisel#5230 · opened on Mar 13, 2026

• Escape FIRRTL Keywords in Emission

  chipsalliance/chisel#5218 · opened on Feb 27, 2026

• Boring from a Probe with U-turn can cause illegal FIRRTL

  chipsalliance/chisel#5130 · opened on Dec 20, 2025
  2

• how to annotations to ltl properties

  chipsalliance/chisel#5118 · opened on Dec 12, 2025
  2

• chisel3.cover drops label in FIRRTL emission

  chipsalliance/chisel#5114 · opened on Dec 9, 2025
  1

• Line up poke() and register output changes in .vcd trace

  chipsalliance/chisel#5107 · opened on Dec 5, 2025
  1

• Chisel 8 Tracker

  chipsalliance/chisel#5100 · opened on Nov 27, 2025

• Adding custom information to Chisel for CIRCT Passes

  chipsalliance/chisel#5078 · opened on Nov 24, 2025
  2

• [chiselsim] stepUntil, but asserting if it doesn't happen?

  chipsalliance/chisel#5077 · opened on Nov 22, 2025

• Naming plugin support for arguments

  chipsalliance/chisel#5061 · opened on Oct 23, 2025
  1

• [Scala3] SouceLine support for VerificationStatement API

  Task

  chipsalliance/chisel#5049 · opened on Oct 7, 2025

• Double-boring can lead to FIRRTL with sink on the RHS of a propassign

  chipsalliance/chisel#5038 · opened on Sep 30, 2025

• HierarchicalModuleName does not work with assert

  chipsalliance/chisel#5001 · opened on Aug 3, 2025
  2