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Status • About • What I Do Best • Projects • Tech Stack • Benchmarks • Writing • Metrics • Connect
| Focus | Details |
|---|---|
| 🔭 Currently Building | High-throughput lock-free Rust data structures (CL-TDS, PulseMap) & Static Analyzers (LineFault) |
| 🛠️ Systems Diagnostics | Spring Boot Graph Analysis & Automated CI Gating (WireDoctor) |
| 🧠 Researching | Bio-inspired cognitive AI & zero-forgetting edge architectures (Project Lethe) |
| 🌱 Learning | RISC-V ISA design & hardware performance counters |
| 💬 Ask Me About | Memory orderings, false-sharing analysis, SIMD vectorization, FFM/FFI & zero-copy I/O |
"Syntax is cheap, intuition is expensive."
I'm a Java and Rust developer, systems engineer, and AI researcher from Jaipur, India, obsessed with pushing hardware to its absolute limits. I enjoy turning "impossible" optimization problems into elegant, high-performance solutions—whether it's building scalable backend systems in Java, writing ultra-efficient low-level code in Rust, or designing bio-inspired AI architectures for edge intelligence.
| Category | Skills |
|---|---|
| ⚡ Performance Optimization | SIMD, Cache Locking, Lock-Free Atomics, Zero-Copy I/O |
| 🦀 Systems Programming | Rust, C++, Low-Level APIs |
| 🔬 Compiler & Static Analysis | AST, HIR, MIR Analysis, LateContext Linting, Monomorphization Hazards (LineFault) |
| 🧠 AI & ML | Bio-Inspired Architectures, Edge AI, Fixed-Memory Systems |
| 🌐 Web & Backend | Rust/Axum, Java/Spring Boot |
| 🔧 Tools & DevOps | Docker, Systemd, Windows Services, Cross-Platform Builds |
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Rust Cache-Line & Memory Ordering Static Analyzer
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Spring Boot Context Diagnostics & CI Gating
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Bio-Inspired Edge AI Continual Learning Engine
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1 MB Cache-Locked Temporal Decay Sketch
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Fixed-Capacity Hash Map with LFU+LRU
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Spring Boot Rate Limiter via FFM & Rust
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Zero-Boilerplate Rust Struct Derive
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Audio Capture & Keyring Daemon
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Tauri 2.0 DWM Stealth & VAD Engine
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Esoteric Hardware Computation
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| Optimization | What I Do With It | Target Metric |
|---|---|---|
| Static Cache Analysis | Detect cache-line false sharing & memory ordering bugs (LineFault) | 0 Compiler ICEs |
| CI Diagnostic Gating | Tarjan SCC dependency graph analysis & context validation (WireDoctor) | Zero Cyclic Deadlocks |
| SIMD Vectorization | Parallelize memory ops via AVX-512 | >100M Ops/sec |
| Cache Locking | Keep data entirely in L3 Cache (1MB max) | Zero Cache Misses |
| Lock-Free Atomics | Zero-mutex concurrent data structures | 0 Lock Contention |
| FFM / FFI | Native Rust bindings for Java 22 / Node.js | <1.2ns Overhead |
| Bio-Inspired Memory | Selective memory decay algorithm (Project Lethe) | 4M Vectors/sec CPU |
- 🦀 Building Lock-Free 1MB Data Structures in Rust
- 🧠 Bio-Inspired AI Memory Architectures: Pushing 4M Vectors/sec on CPU
- ⚡ Java 22 FFM API & Foreign Function Interoperability with Rust
- I once built a hash map that fits entirely in L3 cache (1MB)!
- My favorite optimization rule: "If you don't need it, don't store it."
- I have a secret dream of building a custom RISC-V CPU for streaming data processing.
"The best code is the one that the hardware loves." ✨
— Deendayal Kumawat
Sponsoring supports independent research in bio-inspired AI architectures (Project Lethe) and zero-dependency high-throughput Rust crates.
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