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Report abuseThis repository contains the source code for my Thesis in the Department of Electrical and Computer Engineering at Aristotle University of Thessaloniki. The scope of this project is the employment …
Jupyter Notebook 7
Voice Activity Detection and signal segmentation in time windows. Feature extraction in time and frequency domain. Classification in ten individual speakers.
A set of projects in C and ARM Assembly for the programming of Nucleo STM32. Communication through protocols with peripherals.
C 1
Digital Circuit Design using Verilog in Vivado with a ZedBoard containing a Xilinx ZYNQ®-7000 SoC.
VHDL 8
Some of the projects about PCB design and simulation that I have implemented using Altium Designer
Custom AXI IPs and driving of GPIOs with a ZYNQ-7000 on a ZedBoard
VHDL 3
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