FazBrowse GitHub Viewer | Trending |
URL:
| Home
Tools: [Original HTTPS Page]

Integrated Circuits Lab @ DUTH · GitHub

Integrated Circuits Lab @ DUTH

Research Lab focusing on the design and verification of Digital Integrated Circuits at ECE department of DUTH

Pinned Loading

  1. RISC-V-Vector RISC-V-Vector Public

    Vector processor for RISC-V vector ISA

    SystemVerilog 145 26

  2. DRIM DRIM Public

    DUTH RISC-V Microprocessor

    SystemVerilog 26 10

  3. VQ4SNN VQ4SNN Public

    Vector Quantization for Memory-Efficient FPGA Spiking Neural Networks

    SystemVerilog 2

  4. NoCpad NoCpad Public

    HLS for Networks-on-Chip

    C++ 41 6

  5. FLASH-D FLASH-D Public

    A division-free FlashAttention Implementation.

    C++ 2

Repositories

Loading
Type
Select type
All Public Sources Forks Archived Mirrors Templates
Language
Select language
All C++ SystemVerilog
Sort
Select order
Last updated Name Stars
Showing 10 of 18 repositories

People

This organization has no public members. You must be a member to see who’s a part of this organization.

Top languages

Loading…

Most used topics

Loading…


Back | FazBrowse Home | New Git URL