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Fix SYCL loop auto-configuration - #331
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glesur merged 6 commits intoMar 12, 2025
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unnoticed when a new architecture is tried
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## [2.2.01] 2025-04-16 ### Changed - Fix a bug that led to instabilities in the RKL scheme with very small grid spacings (#323) - Fix a bug that prevented Idefix from running with Sycl backend (required on Intel GPUs) (#331) - Fix an error that led to incorrect electrical current regularisation around the polar axis in non-Ideal MHD (#333) - Improve div(B) checks with a dimensionless implementation, avoiding too large divB errors in grids with large stretch factors (#334) ### Added - Time-Implicit drag for multiple dust species, preventing small time steps for strongly coupled dust grains (#321) - Collisionless heat flux added to the Braginskii module (#317) - New global `idfx::DumpArray` debugging function to dump any Idefix array into a numpy array that can read from python (#318) - Automatic benchmark plots in the documentation (#319) - More CI tests of grid coarsening (#329) - Dump outputs based on wallclock time (#335) --------- Co-authored-by: Victor Réville <victorreville@gmail.com> Co-authored-by: Hal Bal <vreville@irap.omp.eu> Co-authored-by: Jean Kempf <jean.kempf@irap.omp.eu> Co-authored-by: Victor Réville <47865059+vreville@users.noreply.github.com> Co-authored-by: Marc Coiffier <marc.coiffier@univ-grenoble-alpes.fr> Co-authored-by: pre-commit-ci-lite[bot] <117423508+pre-commit-ci-lite[bot]@users.noreply.github.com>
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Following tests in Cambridge with Intel PonteVechio (cf #330)