As an Electronics and Computer Engineering enthusiast, I have specific interests in cutting-edge technologies such as Communication Networks, Robotics, Semiconductors, VLSI Designing and Machine Learning. With an insatiable thirst of knowledge and skill development, I keep pushing my limits in these fields.

I have worked on projects involving Arduino, Raspberry PI, AI/ML (PyTorch), MatLab, KiCAD, LTSpice, Backend Development and small scale applications.

My technical skills include Python (Concepts of OOP, NumPy, Pandas, PyTorch and other libraries such as PIL, MatPlotLib and OpenCV), C (Data Structures and Algorithms), Matlab, SQL, Fusion 360, KiCAD, Arduino IDE and Photoshop.

Beyond my technical acumen, I have a keen eye for capturing the natural beauty of our world through photography. When not tinkering with wires or code, you are likely to find me deep in a game of chess, lost in a good read or playing an intense match of badminton.

My unwavering belief in my potential drives me to excel in any challenge that comes my way. I stick to the quoting "No Resistance can drop my Potential".

If you're interested in collaborating on exciting projects or research, I am always eager to connect.

        

        

        

        

    

1. Handa, N., Gollapalli, A., & Joshi, S. (2025). A Weighted Fault and Congestion Aware Routing Algorithm for Wireless Network-on-Chip Systems. IEEE Networking Letters, 1–1. doi:10.1109/LNET.2025.3636067
   
   Abstract: Wireless network-on-chip (WiNoC) has emerged as a promising solution to address the scalability challenges of traditional wired network-on-chip (NoC) architectures in multi-core processors. This letter presents a novel weighted fault and congestion-aware (WFCA) routing algorithm for WiNoC that combines fault-tolerant algorithms with congestion mitigation strategies. The proposed approach uses a double-sensing mechanism to effectively distribute packets/flits and avoid congested and faulty regions. Simulation results demonstrate that the proposed algorithm enhances system robustness and maintains performance under various fault rates and traffic patterns compared to existing solutions. The algorithm achieves lower latency and higher throughput in high fault scenarios while ensuring low complexity.

2. Gandhi, J., Handa, N., Nayak, A., Diksha Shekhawat, M. Santosh, Jaya Dofe and Pandey, J.G. (2025). SHAKTI: Securing Hardware IPs by Cascade Gated Multiplexer-Based Logic Obfuscation. 2025 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), pp.139–144. doi:10.1109/vlsid64188.2025.00037.
   
   Abstract: The modern distributed chip design chain is increasingly vulnerable to piracy and overproduction. Logic locking has emerged as a prominent solution, allowing chip designers to enhance the security of their hardware intellectual property (IP) by obscuring the functional behavior of the design. Multiplexer (MUX)-based locking is notable for its effectiveness and efficiency. Recent studies have identified its susceptibility to Boolean satisfiability (SAT) and structural learning-based attacks. This article addresses security vulnerabilities and introduces a secure hardware IP design technique with key-controlled cascade gated MUX-based locking (SHAKTI) and its variant SHAKTI+. The proposed techniques integrate a daisy-chained structure and MUXes to improve attack resilience while optimizing resource overhead. The experimental results on ISCAS'85 and ITC'99 benchmark netlists with 64-bit and 128-bit key sizes demonstrate the average area/power/delay overheads for SHAKTI and SHAKTI+ are 19.32/16.35/11.86% and 19.45/17.60/11.56%, respectively. Security evaluations against the SAT attack demonstrated timeouts for all netlists, obstructing key recovery. The average key prediction accuracy for the SCOPE attack on SHAKTI and SHAKTI+ locked designs is only 20.90%. To extend the evaluation, power trace analysis of the locked netlist shows a key-aliasing effect across most locked netlists. The proposed techniques achieve a balanced overhead-security trade-off, strengthening locking against oracle-guided and oracle-less adversarial models.

3. Neuromorphic Engineering : Unleashing Intelligence
   
   Abstract: Dive into the realm of Neuromorphic engineering – an interdisciplinary domain that draws inspiration from the architecture of the human brain. In this riveting exploration, unravel the marvels of brain-inspired computing, a shift from traditional models. Neuromorphic systems emulate parallel processing and distributed memory storage, driving efficiency, adaptability, and intelligence to unprecedented heights. Uncover the ingenious concepts, that fuel this transformation, from Hodgkin-Huxley models to Spiking Neural Networks. While this fascinating journey ignites prospects in robotics, cognitive computing, and beyond, ethical considerations and scalability challenges beckon us to tread thoughtfully.

4. Exploring Flexible Electronics
   
   Abstract: This article delves into the realm of Flexible Electronics, where the convergence of technology and flexibility opens up endless possibilities for applications. It concisely describes all the required information such as Methods, Materials, Applications along with Pros and Cons relating to Flexible Electronics.

5. Self-Healing Code, "Revolutionizing the World of Programming"
   
   Abstract: This article helps in exploring the concept of Self-Healing Code and its potential to enhance software resilience and reliability. It summarizes the complex notion of a code developing itself, and provides resources along with required information for readers to discover the field in greater detail