[proj] GPIO D1 sign-off - #712
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| [OpenTitan hash]: https://github.com/lowRISC/opentitan/tree/bf4a2b24e41742151cfce9c4041e959a3ba76ca3 | ||
| [D1 checklist]: stages.md#d1-design-sign-off-checklist | ||
| [d1-commit]: https://github.com/lowRISC/mocha/commit/b5973217f704923917e7761f73df7dfcb8d0c345 | ||
| [registers]: ../../hw/top_chip/ip_autogen/gpio/doc/registers.md |
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This file is mentioned but it's empty, so I am unsure we can consider SPEC_COMPLETED and/or CSR_DEFINED as done? Can we generate this file easily?
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This is addressed in line 5, and we have an open issue for it that spans a few of the blocks.
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| | RTL | IP_INSTANTIABLE | Done | It is instantiated in top chip system. | ||
| | RTL | PHYSICAL_MACROS_DEFINED_80 | Done | No memory macros or analogue components. | ||
| | RTL | FUNC_IMPLEMENTED | Done | All functionality already implemented. | ||
| | RTL | ASSERT_KNOWN_ADDED | Waived | Output assertions are [here][output asserts]. tl_o and the unused sampled_straps_o have none; signed off in the generated [OpenTitan checklist][ot checklist] and the block is generated without functional changes. The missing assertions will be added as part of [issue #711](https://github.com/lowRISC/mocha/issues/711). |
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I wasn't able to resolve the link properly. Do you mean to make a PR for the missing assertions first?
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| [theory]: ../../hw/top_chip/ip_autogen/gpio/doc/theory_of_operation.md | ||
| [pguide]: ../../hw/top_chip/ip_autogen/gpio/doc/programmers_guide.md | ||
| [ipconfig]: ../../hw/top_chip/ip_autogen/gpio/data/mocha_gpio.ipconfig.hjson | ||
| [output asserts]: ../../hw/top_chip/ip_autogen/gpio/rtl/gpio.sv |
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Please add the exact line range:
| [output asserts]: ../../hw/top_chip/ip_autogen/gpio/rtl/gpio.sv | |
| [output asserts]: ../../hw/top_chip/ip_autogen/gpio/rtl/gpio.sv#L<begin>-L<end> |
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Add the D1 design sign-off checklist for the GPIO and move it to D1 in the stage table.
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Add the D1 design sign-off checklist for the GPIO and move it to D1 in the stage table.