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Report abuseI am an FPGA & Digital Design Engineer based in Munich/Germany.
HDL & Verification
FPGA Tools & Platforms
Embedded & Firmware
FPGA Design & Verification
Embedded Systems
A modular RV32I RISC-V processor core implemented in VHDL for FPGA synthesis and simulation. Project implements a single-cycle, non-pipelined RISC-V processor based on the RV32I base integer instru…
VHDL
A real-time Morse code encoder implementation for the XMC4500 ARM Cortex-M4 microcontroller. This project converts ASCII text strings into visual Morse code signals using precise timing control via…
C
A 32-bit ARM Pipelined Processor Implementation in Verilog HDL along with Forwarding, Hazard Detection, Handling and a Branch Predictor.
Verilog 8
Hardware-based timing side-channel attack for password extraction using XMC4500 ARM Cortex-M4. Exploits keystroke timing variations in password validation systems via USB HID keyboard emulation.
C
Repository with single-cycle, multi-cycle, and pipelined processor designs for architecture labs. Enables study and experimentation to understand processor functionality and performance improvemen…
Verilog
VHDL implementation of the Flancter circuit, a cross-clock-domain handshake mechanism for generating and clearing interrupt requests between an FPGA and microprocessor, featuring toggle-based set/c…
VHDL
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