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marslan6 (Mehmet ARSLAN) · GitHub

  • Munich, Bavaria, Germany
  • 02:06 (UTC +02:00)
  • in/htmos6

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marslan6/README.md

Hi there! 👋 I'm Mehmet Arslan

I am an FPGA & Digital Design Engineer based in Munich/Germany.

  • 🎓 M.Sc. in Communications & Electronics at Technical University of Munich. (Munich/Germany)
  • 🎓 B.Sc. in Electrical & Electronics Engineering from Middle East Technical University. (Ankara/Turkey)

🔧 Skills

HDL & Verification

FPGA Tools & Platforms

Embedded & Firmware


💼 Expertise

FPGA Design & Verification

  • RTL design in VHDL, Verilog, SystemVerilog
  • RISC-V / MIPS processor implementations
  • Verification with UVM, OSVVM, Cocotb
  • Timing closure & resource optimization

Embedded Systems

  • Arm Cortex-M/A firmware (bare-metal & RTOS & embedded C)
  • VxWorks, FreeRTOS, Embedded Linux

📫 Connect

Pinned Loading

  1. Risc-V Risc-V Public

    A modular RV32I RISC-V processor core implemented in VHDL for FPGA synthesis and simulation. Project implements a single-cycle, non-pipelined RISC-V processor based on the RV32I base integer instru…

    VHDL

  2. MORSE-ENCODER MORSE-ENCODER Public

    A real-time Morse code encoder implementation for the XMC4500 ARM Cortex-M4 microcontroller. This project converts ASCII text strings into visual Morse code signals using precise timing control via…

    C

  3. ARM-Pipelined-Processor-With-Branch-Predictor ARM-Pipelined-Processor-With-Branch-Predictor Public

    A 32-bit ARM Pipelined Processor Implementation in Verilog HDL along with Forwarding, Hazard Detection, Handling and a Branch Predictor.

    Verilog 8

  4. Hide-Password Hide-Password Public

    Hardware-based timing side-channel attack for password extraction using XMC4500 ARM Cortex-M4. Exploits keystroke timing variations in password validation systems via USB HID keyboard emulation.

    C

  5. ARM-Processor-Designs ARM-Processor-Designs Public

    Repository with single-cycle, multi-cycle, and pipelined processor designs for architecture labs. Enables study and experimentation to understand processor functionality and performance improvemen…

    Verilog

  6. Flancter Flancter Public

    VHDL implementation of the Flancter circuit, a cross-clock-domain handshake mechanism for generating and clearing interrupt requests between an FPGA and microprocessor, featuring toggle-based set/c…

    VHDL


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