Summary

Sustained TCP receive on the STM32N6 tops out at ~50Mbit/s on a 1Gbit RGMII
link (OpenMV N6), while TCP transmit runs at ~620Mbit/s on the same setup.
The bottleneck is the RX DMA: the 4KB MTL RX FIFO overflows (the MTL RX
queue overflow counter increments) even while free RX descriptors are
available, i.e. the DMA cannot drain the FIFO at line rate.

Three eth changes, one commit each, all scoped to STM32N6:

1. Program the RX DMA burst length. DMACxRXCR.RXPBL was left at its
   reset value of 0, so the RX DMA moves frames out of the FIFO in minimal
   bursts. The TX path already programs a burst length. Set RX to 32 beats.
2. Raise the AXI outstanding-request limits. The DMASBMR read/write
   outstanding-request limit fields reset to one outstanding AXI request,
   which serialises the RX DMA's memory writes. Raise both to the maximum.
3. Skip redundant software RX checksum verification. The N6 MAC is
   configured with checksum offload (MACCR.IPC), and the MTL — in
   store-and-forward mode with forward-error-packets left clear — drops
   checksum-errored frames before the driver sees them. lwip was
   nevertheless re-verifying every RX checksum in software, and since this
   driver runs lwip's input path inside the ETH IRQ handler, that work
   happens at interrupt priority for every frame. Keep only the software
   ICMP checks on STM32N6. Other MCUs don't enable MACCR.IPC and are
   unchanged.

Each register fix was first validated by poking the register live from
Python and watching the MTL overflow counter and throughput respond, then
implemented and re-measured.

A fourth commit fixes a boot-reliability bug found while validating the
above on hardware: some OPENMV_N6 builds of current master fail to boot,
parked in MemManage_Handler before reaching main() with CFSR=IACCVIOL, and
whether a given build boots depends on its code layout. Root cause: this
board boots via a bootloader (mboot or OpenMV's — both supported per the
board's mpconfigboard.mk), and both hand control to the application with
the MPU still enabled (mboot calls mpu_init() itself and
branch_to_application() never disables it; the OpenMV bootloader was
observed handing over with CTRL=ENABLE|HFNMIENA|PRIVDEFENA). mpu_init()
then reprograms MAIR0, region 0 and CTRL while the MPU is live and code is
executing from external XSPI flash — an instruction fetch landing inside
that reconfiguration window takes a spurious MemManage on the Cortex-M55.
The fix disables the MPU (with barriers) and clears every region before
configuring it, so initialization starts from a defined state.

Performance on an OpenMV N6 (1Gbit RGMII link, Python socket benchmark
with preallocated buffers and 64KB readinto, same board/host/switch,
8 runs across two build layouts):

Testing

Tested on an OpenMV N6 (STM32N657, RGMII, 1Gbit link) running this
branch's OPENMV_N6 build: Python socket benchmarks for TCP/UDP in both
directions (numbers above), plus hardware-counter verification that the
MTL RX FIFO overflow counter stops incrementing under sustained TCP RX
after the register changes.

The MPU fix was verified by flashing a master build that faults on every
boot (MemManage before main) and confirming the same source with this fix
boots cleanly across repeated reset cycles; the full branch was also
boot-cycled and re-benchmarked on top of the fix.

An STM32H747 board (Arduino Portenta H7, 100Mbit RMII link) was
runtime-tested with the same benchmark suite: ~line rate (TCP RX 91.1 /
TCP TX 80.9 / UDP TX 87.5 / UDP RX ~95 Mbit/s), identical with and without
the checksum change — consistent with the H7 not being RX-CPU-bound at
100Mbit. The eth changes are all N6-scoped: the H7 (like F4/F7) does not
enable MACCR.IPC, so its software checksum verification is retained.

Build-tested: OPENMV_N6, NUCLEO_H563ZI (shares the ARMv8-M
mpu_init()), NUCLEO_H743ZI, NUCLEO_F767ZI (the second eth commit
restructures a #if shared with the H5/H7 path).

Trade-offs and Alternatives

No RAM and negligible code-size cost — the eth changes are register
configuration and a compile-time lwip checksum setting; the MPU change
adds a short clear-all-regions loop at init.

The remaining gap to line rate on TCP RX is the RX ring depth: lwip's
input path runs under the lwip lock (which masks the ETH IRQ during
Python-side socket operations), and when the 16-entry RX ring fills during
those windows the FIFO overflows again. Deepening the ring from 16 to 48
entries was measured at ~234 Mbit/s TCP RX (~4.7×) but costs 48KB of RAM,
so it is deliberately not included; it could be exposed later as a
board-configurable option (e.g. MICROPY_HW_ETH_RX_BUF_NUM) for boards
willing to spend the RAM.

The MPU commit is independent of the eth commits and can be split into its
own PR if preferred.

Generative AI

I used generative AI tools when creating this PR, but a human has checked
the code and is responsible for the code and the description above.