Tracking issue for porting multikernel to RISC-V. Companion to the arm64 tracking issue #21; the generic-core cleanups in #8 are a shared prerequisite.

Evaluation summary

RISC-V is the easiest of the three architectures on the CPU side. S-mode kernels never own the hart lifecycle; SBI HSM does, and Linux already drives hotplug through it (cpu_ops_sbi.c). HART_START(hartid, addr, opaque) enters with satp = 0, interrupts masked, a0 = hartid, a1 = opaque, which is exactly the Linux boot protocol (a0 = hartid, a1 = DTB). So:

• pool = HSM STOPPED state, a parked hart executes nothing;
• primary boot trampoline = one HART_START ecall;
• spawn secondaries use stock sbi_cpu_start() / sbi_cpu_stop();
• confirm-parked = HART_STATUS == STOPPED;
• no inherited CPU state, no identity page tables, no repark bookkeeping.

Two sharp edges arm64 does not have:

1. Stale I-cache on re-spawn: no remote I-cache invalidation, _start_kernel does not fence.i in S-mode, OpenSBI does not invalidate on HART_START. Fix: a constant fence.i; jr entry stub in the ctrl block, the only multikernel assembly RISC-V needs.
2. SRST resets the whole machine: a spawn running stock machine_halt()/reboot powers off the host. The HART_STOP-everywhere override is a prerequisite for the first spawn that reaches userspace.

Interrupts partition by source (PLIC contexts, APLIC sourcecfg/target). IMSIC has one interrupt file per hart, so MSI is a direct write and the spawn composes MSI messages itself: the arm64 host-proxied ITS (#16) has no RISC-V counterpart. What RISC-V lacks is a forced-halt primitive: no S-mode NMI, and SBI SSE (the fix) is not in the tree yet.

Full write-up: /tmp/multikernel-riscv-design.md (includes an x86 / arm64 / RISC-V comparison table).

Tasks, in dependency order

Foundation

• arm64 prep: remove x86-isms from generic multikernel core #8 remove x86-isms from the generic core (shared with arm64)
• riscv: Kconfig, asm/multikernel.h (hartid maps) and arch stubs #22 Kconfig, asm/multikernel.h, arch stubs

CPU lifecycle (small, low risk; #23, #24, #25 land together)

• riscv: SBI HSM based spawn, confirm-parked and release #23 SBI HSM spawn / confirm-parked / release
• riscv: fence.i entry stub to avoid stale I-cache on re-spawn #24 fence.i entry stub (stale I-cache on re-spawn)
• riscv spawn: halt/reboot must HART_STOP every hart, never SRST #25 spawn halt/reboot must HART_STOP, never SRST
• riscv: KEXEC_TYPE_MULTIKERNEL Image loader, placement in the grant, no purgatory #26 KEXEC_TYPE_MULTIKERNEL Image loader, no purgatory

Boot data and messaging

• riscv: instance DTB filtering (DT host), synthesis for ACPI hosts later #27 instance DTB filtering (DT host), synthesis later
• riscv: multikernel doorbell (IMSIC identity or SBI IPI convention) #28 doorbell (IMSIC identity or SBI IPI convention)

Milestone A: device-less spawn boots on its own harts and memory with earlycon=sbi, exchanges ring messages, halts gracefully, survives a 50x re-spawn loop.

Interrupts (pick by target platform)

• riscv: PLIC tenant mode (own contexts, granted sources only) #29 PLIC tenant mode
• riscv: APLIC tenant mode and per-hart IMSIC MSI for spawn kernels #30 APLIC tenant mode + per-hart IMSIC MSI

Milestone B: an assigned PCIe device with MSI works in a spawn (QEMU aia=aplic-imsic first).

Robustness and isolation

• riscv: forced halt, best-effort IPI now, SBI SSE when available #31 forced halt: best-effort IPI now, SBI SSE when merged
• riscv: IOMMU bypass / second-stage containment for assigned devices #32 IOMMU bypass / second-stage containment
• riscv: OpenSBI domains, diagnose unreachable harts and document static-partition mode #33 OpenSBI domains: diagnose unreachable harts, document static-partition mode

Optional

• riscv: spinwait / M-mode fallback park page (optional) #34 spinwait / M-mode fallback park page

Infrastructure

• riscv: QEMU virt + OpenSBI test environment, kerf support and docs #35 QEMU virt + OpenSBI environment, kerf support, docs

Targets: QEMU virt with OpenSBI (aia=none and aia=aplic-imsic), then SG2042 (Milk-V Pioneer, 64 harts, PLIC, PCIe).