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DNN Compiler for Heterogeneous SoCs
Python 75 48
A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
Tcl 127 34
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
Verilog 363 115
An energy-efficient RISC-V floating-point compute cluster.
C 146 115
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
SystemVerilog 1.7k 368
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
C 538 196
This is the fork of CVA6 intended for PULP development.
Build GNU/Linux for various PULP/Cheshire-based systems.
This is the repository for CachePool architecture for the ManyRVData project
An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
Collection of peripheral IPs using the Open Bus Interface (OBI)
Reusable IPs targetting student tapeouts based on the Croc SoC.
An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders
aka Lago-Mio
Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
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