A from-scratch emulator for Raspberry Pi RP2040 and RP2350 microcontrollers, supporting both ARM Cortex-M0+ (Thumb) and RISC-V Hazard3 (RV32IMAC) cores. Loads and executes UF2 and ELF firmware with accurate memory mapping and peripheral emulation.

319 tests passing (zero warnings). RP2040: Complete — boots MicroPython, CircuitPython, littleOS. RP2350 RISC-V: Complete Hazard3 emulation with Zba, Zbb, Zbs, Zcb, Zcmp, and Zbkb extensions. Boots MicroPython Pico 2 RISC-V and SagePico REPL with full semihosting I/O. RP2350 ARM: Cortex-M33 mode (-arch m33) with RP2350 ROM format and clock-domain peripheral address mapping. Boots to TinyUSB init. Tri-architecture: -arch m0+ / -arch m33 / -arch rv32 with automatic firmware detection via UF2 family ID and picobin IMAGE_DEF blocks. Networking: Virtual network bus with TAP bridge, multi-instance Ethernet mesh, W5500 live sockets, and software-defined devices.

Both devices attach via spi_attach_device() callbacks with periodic flush and flush-on-exit.

All peripherals support RP2040 atomic register aliases (SET/CLR/XOR).

• Cycle timing: Default 1 MHz (fast-forward). Use -clock 125 for real RP2040 timing.
• Fidelity tradeoffs: DMA pacing, very high-speed PIO timing, and non-CDC USB device behavior are still functional models rather than fully cycle-perfect hardware.
• See ROADMAP for detailed status.

• CMake 3.10+
• Standard C library (host)
• arm-none-eabi-gcc and Python 3 if you want to build the sample/test firmware

./build.sh

This builds the bramble executable in the project root.

You can also build explicitly with CMake:

cmake -S . -B build
cmake --build build -j

Bramble builds with dual-core support enabled by default. Select the active cores at runtime:

./bramble firmware.uf2 -cores 1
./bramble firmware.uf2 -cores 2
./bramble firmware.uf2 -cores auto

Hello World (prints "Hello from ASM!"):

cd test-firmware
chmod +x build.sh
./build.sh hello_world

GPIO Test (toggles LED on GPIO 25):

cd test-firmware
./build.sh gpio

Timer Test (measures elapsed time):

cd test-firmware
./build.sh timer

Alarm Test (tests timer alarms):

cd test-firmware
./build.sh alarm

Interactive UART Prompt Test (reads host stdin via -stdin and prints a greeting):

cd test-firmware
./build.sh name_prompt

Build All Tests:

cd test-firmware
./build.sh all

UF2 Firmware:

./bramble hello_world.uf2
./bramble gpio_test.uf2
./bramble timer_test.uf2
./bramble alarm_test.uf2
./bramble name_prompt.uf2 -stdin
printf 'Ada\n' | ./bramble name_prompt.uf2 -stdin

ELF Firmware (auto-detected by extension):

./bramble firmware.elf

ctest --test-dir build --output-on-failure

Bramble now supports flexible debug output modes:

Single-Core CPU Step Tracing (verbose CPU and peripheral logging):

./bramble -debug timer_test.uf2

Assembly Instruction Tracing (detailed POP/BX/branch operations):

./bramble -asm alarm_test.uf2

Combined Debug + Assembly Tracing:

./bramble -debug -asm alarm_test.uf2

No Debug Output:

./bramble hello_world.uf2

Dual-Core Specific:

./bramble firmware.uf2 -debug           # Core 0 debug output
./bramble firmware.uf2 -debug -debug1   # Both cores debug
./bramble firmware.uf2 -status          # Periodic status updates
./bramble firmware.uf2 -debug -status   # Debug + status combined
./bramble firmware.uf2 -stdin           # Route stdin to USB CDC when active, else UART0
./bramble firmware.uf2 -gdb            # Start GDB server on port 3333
./bramble firmware.uf2 -gdb 4444       # GDB server on custom port
./bramble firmware.uf2 -clock 125      # Real RP2040 timing (125 MHz)
./bramble firmware.uf2 -flash fs.bin   # Persistent flash storage
./bramble firmware.uf2 -debug-mem      # Log unmapped peripheral access
./bramble firmware.uf2 -jit            # Enable JIT for hot flash/ROM loops
./bramble firmware.uf2 -cores 2 -thread-quantum 128  # Tune threaded timeslice

RP2350 RISC-V Mode:

# Explicit architecture selection
./bramble firmware_rv.uf2 -arch rv32

# Auto-detected from UF2 family ID (0xE48BFF5A) or ELF machine type
./bramble pico2_rv_firmware.uf2

# With clock speed and flash persistence
./bramble firmware_rv.uf2 -arch rv32 -clock 150 -flash rv_flash.bin -stdin

Networking (UART-to-TCP bridge):

# Bridge UART0 to TCP port (connect with nc, minicom, etc.)
./bramble firmware.uf2 -net-uart0 9999 -stdin
# In another terminal: nc localhost 9999

# Connect UART0 to a remote host
./bramble firmware.uf2 -net-uart0-connect 192.168.1.10:9999

Multi-Device Wiring (inter-instance communication):

# Terminal 1: Instance A with UART0 wired via Unix socket
./bramble fw_sensor.uf2 -wire-uart0 /tmp/uart_link.sock -stdin

# Terminal 2: Instance B with UART0 wired to the same socket
./bramble fw_controller.uf2 -wire-uart0 /tmp/uart_link.sock -stdin

# UART TX on either side arrives as UART RX on the other
# GPIO pins can also be wired: -wire-gpio /tmp/gpio_link.sock

WiFi (Pico W / CYW43):

# Basic Pico W/CYW43 emulation
./bramble firmware.uf2 -wifi

# Bridge emulated WLAN frames to a host TAP interface
./bramble firmware.uf2 -wifi -tap tap0

Virtual Network (Internet Bridge + Mesh):

# Single-command internet bridge (auto-creates TAP, NAT, sudo)
./bramble firmware.uf2 -net -stdin

# Mesh two Bramble instances via Ethernet-level peer link
./bramble fw1.uf2 -net-peer /tmp/vnet.sock -stdin   # Terminal 1
./bramble fw2.uf2 -net-peer /tmp/vnet.sock -stdin   # Terminal 2

# W5500 live networking (real host TCP/UDP sockets)
./bramble w5500_firmware.uf2 -net -net-live -stdin

# Wire Ethernet frames between instances
./bramble fw_sensor.uf2 -wire-eth /tmp/mesh.sock -stdin
./bramble fw_ctrl.uf2 -wire-eth /tmp/mesh.sock -stdin

Software-Defined Devices (SDD):

# Attach a TMP102 thermometer on I2C0 at 0x48
./bramble firmware.uf2 -sdd thermometer

# Custom temperature, bus, and address
./bramble firmware.uf2 -sdd thermometer:temp=37.5,i2c=1,addr=0x49

# Combine with mesh networking
./bramble fw_sensor.uf2 -wire-eth /tmp/mesh.sock -sdd thermometer:temp=42

Storage Devices (SD Card / eMMC):

# Attach a 32MB SD card image on SPI1 (default)
./bramble firmware.uf2 -sdcard sdcard.img -sdcard-size 32

# Attach SD card on SPI0 instead
./bramble firmware.uf2 -sdcard sdcard.img -sdcard-spi 0

# Attach a 64MB eMMC image on SPI0 (default)
./bramble firmware.uf2 -emmc emmc.img -emmc-size 64

# Attach eMMC on SPI1 instead
./bramble firmware.uf2 -emmc emmc.img -emmc-spi 1

# Combine with flash persistence and MicroPython
./bramble python/micropython.uf2 -stdin -clock 125 -flash mpy.bin -sdcard sd.img

MicroPython REPL:

./bramble python/micropython.uf2 -stdin -clock 125 -flash mpy.bin

Output:

MicroPython v1.27.0 on 2025-12-09; Raspberry Pi Pico with RP2040
Type "help()" for more information.
>>>

GDB Remote Debugging:

# Terminal 1: Start emulator with GDB server
./bramble firmware.uf2 -gdb

# Terminal 2: Connect GDB
arm-none-eabi-gdb firmware.elf -ex "target remote :3333"

Expected output:

╔════════════════════════════════════════════════════════════╗
║       Bramble RP2040 Emulator - Dual-Core Mode           ║
╚════════════════════════════════════════════════════════════╝

[Init] Initializing dual-core RP2040 emulator...
[Init] Loading firmware: littleOS.uf2
[Init] Firmware loaded successfully
[Boot] Starting Core 0 from flash...
[Boot] Core 0 SP = 0x20020000
[Boot] Core 0 PC = 0x10000104
[Boot] Core 1 held in reset (waiting for Core 0 to start)

═══════════════════════════════════════════════════════════
Executing...
═══════════════════════════════════════════════════════════

Bramble/
├── src/
│   ├── main.c          # Unified entry point, boot, execution (single & dual)
│   ├── cpu.c           # Cortex-M0+ core: O(1) dispatch, dual-core, exceptions
│   ├── instructions.c  # 60+ Thumb instruction implementations
│   ├── membus.c        # Memory bus: pointer-based routing, peripheral stubs
│   ├── elf.c           # ELF32 ARM binary loader
│   ├── uf2.c           # UF2 file loader
│   ├── gpio.c          # GPIO peripheral emulation
│   ├── timer.c         # Hardware timer emulation
│   ├── nvic.c          # NVIC interrupt controller
│   ├── clocks.c        # Resets, Clocks, XOSC, PLLs, Watchdog
│   ├── adc.c           # ADC peripheral emulation
│   ├── rom.c           # ROM function table with Thumb code stubs
│   ├── uart.c          # Dual PL011 UART emulation
│   ├── spi.c           # Dual PL022 SPI emulation
│   ├── i2c.c           # Dual DW_apb_i2c emulation
│   ├── pwm.c           # 8-slice PWM emulation
│   ├── dma.c           # 12-channel DMA controller
│   ├── pio.c           # Dual PIO block emulation (full instruction execution)
│   ├── usb.c           # USB controller with host enumeration + CDC bridge
│   ├── rtc.c           # RTC peripheral (ticking, calendar, leap year)
│   ├── gdb.c           # GDB remote serial protocol stub
│   ├── netbridge.c     # UART-to-TCP bridge
│   ├── wire.c          # Multi-instance Unix socket wiring
│   ├── vnet.c          # Virtual network bus (TAP/peer/port routing)
│   ├── sdd.c           # Software-defined device framework
│   ├── sdd_thermo.c    # TMP102 I2C thermometer device model
│   ├── storage.c       # Flash write-through persistence
│   ├── sdcard.c        # SD card SPI emulation (SDHC, file-backed)
│   ├── emmc.c          # eMMC SPI emulation (file-backed)
│   ├── fatfs.c         # FAT16 helpers for flash/FUSE
│   ├── fuse_mount.c    # Optional FUSE mount integration
│   ├── w5500.c         # W5500 Ethernet device model
│   ├── bme280.c        # BME280 sensor model
│   ├── corepool.c      # Host-threaded execution + core allocation
│   ├── cyw43.c         # CYW43 WiFi emulation
│   ├── tapif.c         # TAP bridge for Pico W traffic
│   ├── devtools.c      # Developer tools (semihosting, coverage, etc.)
│   └── rp2350_rv/
│       ├── rv_cpu.c    # Hazard3 RV32IMAC CPU engine (93 instructions)
│       ├── rv_clint.c  # CLINT interrupt controller (mtime/mtimecmp/MSIP)
│       ├── rv_membus.c # RP2350 memory bus (520KB SRAM, peripheral routing)
│       └── rv_bootrom.c # Minimal RISC-V bootrom
├── include/
│   ├── emulator.h      # Core definitions, CPU state, memory layout
│   ├── instructions.h  # Instruction handler prototypes
│   ├── gpio.h          # GPIO register definitions
│   ├── timer.h         # Timer register definitions
│   ├── nvic.h          # NVIC register definitions
│   ├── clocks.h        # Clock-domain peripheral definitions
│   ├── adc.h           # ADC register definitions
│   ├── rom.h           # ROM layout and function codes
│   ├── uart.h          # PL011 UART register definitions
│   ├── spi.h           # PL022 SPI register definitions
│   ├── i2c.h           # DW_apb_i2c register definitions
│   ├── pwm.h           # PWM register definitions
│   ├── dma.h           # DMA controller register definitions
│   ├── pio.h           # PIO register definitions
│   ├── usb.h           # USB controller register definitions
│   ├── rtc.h           # RTC register definitions
│   ├── gdb.h           # GDB RSP stub definitions
│   ├── netbridge.h     # UART network bridge definitions
│   ├── wire.h          # Multi-instance wire protocol definitions
│   ├── vnet.h          # Virtual network bus definitions
│   ├── sdd.h           # Software-defined device definitions
│   ├── storage.h       # Flash write-through definitions
│   ├── sdcard.h        # SD card SPI definitions
│   ├── emmc.h          # eMMC SPI definitions
│   ├── fatfs.h         # FAT filesystem helpers
│   ├── fuse_mount.h    # FUSE mount definitions
│   ├── w5500.h         # W5500 device definitions
│   ├── bme280.h        # BME280 device definitions
│   ├── corepool.h      # Core pool definitions
│   ├── cyw43.h         # CYW43 WiFi definitions
│   ├── tapif.h         # TAP bridge definitions
│   ├── devtools.h      # Developer tools definitions
│   ├── rp2350_rv/
│   │   ├── rv_cpu.h        # RISC-V CPU state, CSR defs, instruction decode
│   │   ├── rv_clint.h      # CLINT interrupt controller definitions
│   │   ├── rv_membus.h     # RP2350 memory bus definitions
│   │   ├── rv_bootrom.h    # Bootrom generator definitions
│   │   └── rp2350_memmap.h # RP2350 memory map constants
│   └── rp2350_arm/
│       └── m33_cpu.h       # Cortex-M33 placeholder
├── tests/
│   └── test_suite.c    # Unit test suite (319 tests, verbose, CTest integrated)
├── test-firmware/
│   ├── hello_world.S   # Assembly UART test
│   ├── gpio_test.S     # Assembly GPIO test
│   ├── timer_test.S    # Assembly timer test
│   ├── alarm_test.S    # Assembly alarm test
│   ├── interrupt_test.S # Assembly interrupt test
│   ├── linker.ld       # Memory layout definition
│   ├── uf2conv.py      # UF2 conversion utility
│   └── build.sh        # Firmware build script
├── docs/
│   ├── GPIO.md         # GPIO peripheral documentation
│   ├── NVIC_audit_report.md # NVIC audit findings and recommendations
│   └── ROADMAP.md      # Development roadmap and feature status
├── CMakeLists.txt      # Build configuration
├── build.sh            # Top-level build script
├── CHANGELOG.md        # Version history and changes
└── README.md           # This file

• 64-bit Counter: Microsecond-resolution time tracking
• 4 Independent Alarms: ALARM0-3 with configurable trigger points
• Interrupt Generation: Sets INTR bits when alarms fire and signals NVIC IRQ 0-3 when enabled
• Write-1-to-Clear: Standard ARM interrupt acknowledgment
• Pause/Resume: Stop timer for debugging
• Atomic Operations: Armed register shows active alarms

• TIMER_TIMELR/TIMEHR (0x4005400C/08): Read 64-bit counter
• TIMER_TIMELW/TIMEHW (0x40054004/00): Write 64-bit counter
• TIMER_ALARM0-3 (0x40054010-1C): Set alarm compare values
• TIMER_ARMED (0x40054020): Shows which alarms are active
• TIMER_INTR (0x40054034): Raw interrupt status (W1C)
• TIMER_INTE (0x40054038): Interrupt enable mask
• TIMER_INTS (0x40054040): Masked interrupt status

/* Read current time */
ldr r0, =0x4005400C      /* TIMER_TIMELR */
ldr r1, [r0]             /* R1 = current time in microseconds */

/* Set alarm for 1000us in future */
ldr r2, =1000
add r1, r2               /* R1 = target time */
ldr r0, =0x40054010      /* TIMER_ALARM0 */
str r1, [r0]             /* Alarm armed automatically */

/* Wait for alarm (polling) */
poll:
    ldr r0, =0x40054034  /* TIMER_INTR */
    ldr r1, [r0]
    movs r2, #1
    tst r1, r2           /* Check bit 0 */
    beq poll

/* Clear interrupt */
movs r1, #1
ldr r0, =0x40054034      /* TIMER_INTR */
str r1, [r0]             /* Write 1 to clear */

• 30 GPIO Pins (GPIO 0-29, matching RP2040)
• SIO Fast Access: Direct read/write at 0xD0000000
• Atomic Operations: SET, CLR, XOR registers for thread-safe bit manipulation
• Function Select: All 10 GPIO functions (SIO, UART, SPI, I2C, PWM, PIO0/1, etc.)
• Per-Pin Configuration: Control and status registers via IO_BANK0
• Pad Control: Pull-up/down, drive strength via PADS_BANK0
• Interrupt Support: Full edge/level detection with NVIC delivery (IRQ 13)

/* Configure GPIO 25 as output (LED on Pico) */
ldr r0, =0x400140CC      /* GPIO25_CTRL */
movs r1, #5              /* Function 5 = SIO */
str r1, [r0]

/* Enable output */
ldr r0, =0xD0000024      /* SIO_GPIO_OE_SET */
ldr r1, =(1 << 25)       /* Bit 25 */
str r1, [r0]

/* Turn LED on */
ldr r0, =0xD0000014      /* SIO_GPIO_OUT_SET */
str r1, [r0]

See docs/GPIO.md for complete documentation.

• Independent Core Execution: Both cores run independently with their own:

  • Program counters (PC)
  • Stack pointers (SP)
  • Register sets (R0-R12, LR)
  • Debug flags (-debug, -debug1)

• Memory Sharing:

  • Flash (2 MB): Shared and execute-only
  • Core 0 RAM (128 KB): 0x20000000 - 0x2001FFFF
  • Core 1 RAM (128 KB): 0x20020000 - 0x2003FFFF
  • Shared RAM (64 KB): 0x20040000 - 0x2004FFFF

• Inter-Core Communication:

  • Dual FIFOs: Core 0 ↔ Core 1 messaging
  • Spinlocks: Hardware-level synchronization (32 spinlocks)
  • SIO Atomic Operations: Thread-safe bit manipulation

Flash:            0x10000000 - 0x10200000  (2 MB, shared)
Core 0 RAM:       0x20000000 - 0x20020000  (128 KB, core-local)
Core 1 RAM:       0x20020000 - 0x20040000  (128 KB, core-local)
Shared RAM:       0x20040000 - 0x20050000  (64 KB, shared)
Total RAM:        320 KB usable, 264 KB available

// In C firmware code for dual-core operation:

// Core 0: Send message to Core 1
fifo_push(CORE0, 0x12345678);

// Core 1: Receive message
uint32_t msg = fifo_pop(CORE1);

// Both cores: Synchronized access to shared memory
spinlock_acquire(0);
shared_counter++;
spinlock_release(0);

Most firmware builds naturally for dual-core:

# In your firmware makefile:
make CORES=2  # Compiles with dual-core definitions

Then run with:

./bramble firmware.uf2 -status  # Show status for both cores

The emulator accurately models the RP2040 address space:

• Flash (XIP): 0x10000000 - 0x101FFFFF (2MB executable, + aliases at 0x11/0x12/0x13)
• XIP Cache Control: 0x14000000 (CTRL, FLUSH, STAT, counters)
• XIP SRAM: 0x15000000 - 0x15003FFF (16KB cache as SRAM)
• SRAM: 0x20000000 - 0x20041FFF (264KB, + mirror alias at 0x21000000)
• APB Peripherals: 0x40000000 - 0x4FFFFFFF (UART, GPIO, timers, etc.)
• SIO: 0xD0000000 - 0xD0000FFF (Single-cycle I/O, GPIO fast access)

All accesses respect alignment requirements and return appropriate values for unimplemented regions.

Peripherals are integrated into the memory bus (membus.c):

• Reads/writes to peripheral address ranges are routed to peripheral modules
• GPIO: 0x40014000 (IO_BANK0), 0x4001C000 (PADS), 0xD0000000 (SIO)
• Timer: 0x40054000 (64-bit counter, 4 alarms, interrupts)
• UART: 0x40034000 / 0x40038000 (PL011 dual)
• SPI: 0x4003C000 / 0x40040000 (PL022 dual)
• I2C: 0x40044000 / 0x40048000 (DW_apb_i2c dual)
• PWM: 0x40050000 (8 slices)
• DMA: 0x50000000 (12 channels with chaining)
• PIO: 0x50200000 / 0x50300000 (2 blocks, 4 SMs each, full instruction execution)
• XIP Cache: 0x14000000 (CTRL, FLUSH, STAT, counters, stream)
• XIP SRAM: 0x15000000 (16KB cache as SRAM)
• ROM: 0x00000000 (16KB with function table and Thumb code)

The timer uses a cycle-accurate timing model with configurable clock frequency:

• Default: 1 MHz (1 cycle = 1 µs, fast-forward mode for speed)
• Real RP2040: 125 MHz (-clock 125, 125 cycles per microsecond)
• Each instruction costs 1-4+ CPU cycles based on the ARMv6-M instruction timing table
• A cycle accumulator converts CPU cycles to microseconds for the timer
• SysTick counts in raw CPU cycles (correct per ARM Cortex-M specification)

Alarms trigger when:

if (timer_low_32bits >= alarm_value) {
    set_interrupt_bit();
    disarm_alarm();
}

Instructions are dispatched via a 256-entry O(1) lookup table indexed by instr >> 8:

1. 32-bit instructions (BL/BLX, MSR/MRS, DSB/DMB/ISB) detected by top-5-bit check and handled before table lookup
2. 16-bit instructions dispatched via dispatch_table[instr >> 8](instr) in constant time
3. Secondary dispatchers handle entries where multiple instructions share the same top byte (ALU block 0x40-0x43, hints 0xBF, etc.)
4. pc_updated flag: Handlers that modify PC set this flag; cpu_step() auto-advances PC by 2 only if unset

The emulator implements full APSR flag semantics:

• N (Negative): Bit 31 of result
• Z (Zero): Result equals zero
• C (Carry): Unsigned overflow (for ADD) or NOT borrow (for SUB)
• V (Overflow): Signed overflow (operands same sign, result different)

Helper functions update_add_flags() and update_sub_flags() ensure consistency across all arithmetic instructions.

The UF2 loader validates:

• Magic numbers (0x0A324655, 0x9E5D5157, 0x0AB16F30)
• Target address in flash range
• Payload size bounds (up to 476 bytes per block)
• Overflow-safe target calculations before writing to flash

Multi-block firmware images are supported with sequential loading, and malformed or out-of-range blocks are rejected without modifying flash.

Core Synchronization:

• Both cores execute independently in the main loop
• dual_core_step() advances both cores one instruction each
• any_core_running() checks if either core is still executing
• Shared state (memory, peripherals) is automatically synchronized

FIFO Implementation:

typedef struct {
    uint32_t buffer[FIFO_DEPTH];  // 8 entries per FIFO
    uint16_t write_ptr;
    uint16_t read_ptr;
    uint16_t count;
} fifo_t;

Spinlock Implementation:

uint32_t spinlock_acquire(uint32_t lock_id) {
    if (spinlocks[lock_id] & SPINLOCK_LOCKED) {
        return 0;
    }
    spinlocks[lock_id] = SPINLOCK_VALID | SPINLOCK_LOCKED;
    return 1u << lock_id;
}

Bramble now ships with a 64K decoded instruction cache enabled by default and optional JIT basic-block compilation via -jit.

• Instruction cache: Avoids repeat decode/dispatch work for hot Thumb-1 paths.
• JIT: Compiles hot flash/ROM basic blocks and reports execution stats on exit.
• Threaded execution: -cores 2 and -cores auto map emulated cores to host pthreads while preserving a shared-state lock.
• I/O behavior: Firmware output stays on stdout while emulator diagnostics stay on stderr, which keeps pipes and scripted runs predictable.

For benchmarking details, see tests/benchmark.c.

1. Timing fidelity: DMA pacing, high-speed PIO timing, and more USB edge cases.
2. Device breadth: More SPI/I2C SDD models (accelerometers, displays, EEPROMs).
3. Tooling: More firmware examples, benchmarks, and workflow automation around regression testing.
4. Networking depth: DHCP server in vnet, mDNS relay, packet capture/replay tooling.

The Bramble project is open for contributions! Areas that need help:

1. Testing: Firmware coverage, edge cases, and performance benchmarks.
2. Device models: Sensors, networking peripherals, and board-specific integrations.
3. Documentation: Register descriptions, usage examples, architecture guides

Run ctest --test-dir build --output-on-failure to verify changes don't break existing tests. See CHANGELOG.md for release history and docs/ for detailed technical documentation.

MIT License - See LICENSE file for details

For issues, questions, or contributions:

• Open an issue on GitHub
• Check existing documentation in docs/
• Review CHANGELOG.md for recent changes
• See NVIC Audit Report for historical background on early NVIC issues