…vert GGUF

…re-tokenizer

Qwen/Qwen3.5-4B is Qwen3_5ForConditionalGeneration (multimodal). Without this
mapping neither the target nor the DFlash drafter converts to GGUF.

The DFlash drafter targets a Gated-DeltaNet hybrid (recurrent + attention). The
recurrent state can't be partial-rolled-back, so a naive verify is slower than
plain generation. This brings it to lossless speedup:

- recurrent-state rewind via a per-token GDN state trace + on-device promote of
  the accepted state (llama_dflash_promote_state) instead of a ~50 MiB host
  checkpoint and re-decode per round
- graph reuse: fixed-capacity device-resident target-context cache, encoder
  folded into the decoder graph, padding mask over a bucketed context
- on-device greedy verify: drafter block argmax + target argmax for the greedy
  verify (llama_set_out_argmax), one host sync per round
- optional GPU sampling verify (temperature; top-k/top-p behind LLAMA_SPEC_GPU_SAMPLE)
- CUDA graphs opt-in on Volta (GGML_CUDA_GRAPHS_VOLTA) and a stable sched uid

Lossless. ~1.7x on V100/Q8 single-stream, scaling with the draft block on
high-acceptance (reasoning) workloads.

Decompose the GDN recurrence into a pure ggml-op graph (cumsum, exp, mul_mat,
tri, solve_tri, diag, concat) so the verify can run on backends that lack a
fused GDN kernel (WebGPU, Metal, Vulkan). Multi-chunk tiling keeps exp(cumsum(g))
in fp32 range; handles both the vector (KDA) and per-head scalar gate, and GQA.

Validated bitwise against ggml_gated_delta_net on CPU and CUDA
(tests/test-gdn-chunked). Opt-in via LLAMA_GDN_CHUNKED; the default path is
unchanged. This is for portability: on CUDA the fused kernel is faster and the
GDN scan is not the verify bottleneck.

The server DFlash path was wired but crashed on every request, because the
server processes a prompt in several ubatches while speculative-simple does it
in one decode:

- index the target features by absolute position and accumulate across ubatches
  (a chunked prompt previously left the first draft reading stale features), and
  read the [n_total-n_new, n_total) slice in the drafter
- reset dflash_n_past per request in begin() (it carried over between requests)
- set the view buffers in dflash_promote_state so the trace/promote copy also
  runs on the CPU backend (was a CUDA-only path, asserted on a null buffer)

Also add GPU greedy verify: for a pure-greedy request the target emits an
on-device argmax of the verify block and the host skips the per-block logits
download + CPU sampler. Enabled only after the first token is sampled from
logits, reset per request; non-greedy requests fall back to the host sampler.

Lossless (byte-identical to the host-verify path). ~2.0x -> 2.4x on reasoning.

- Read nextn_predict_layers from GGUF KV; set n_layer_kv_from_start
- Fix recurrent_layer_arr: MTP blocks (i >= main_layers) are always
  full-attention (not recurrent), only main blocks use the 4-cycle rule
- Use main_layers count (not n_layer) for LLM_TYPE detection
- Register all blk.N.nextn.* and blk.N.attn_*/ffn_* tensors for nextn
  blocks with TENSOR_SKIP (loaded but unused in main forward pass,
  consistent with GLM4_MOE pattern)
- Add NEXTN tensor names to QWEN35MOE arch in gguf/constants.py

Companion file mtp-SIQ-1-35B.f16.gguf (block 40, from Qwen3.6-35B-A3B)
uploaded to AlexWortega/SIQ-1-35B; merge with merge_mtp_gguf.py.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>