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1. TAGE-Branch-Predictor-with-RISC-V TAGE-Branch-Predictor-with-RISC-V Public

   Implementation of TAGE and GShare branch predictors for the CVA6 (Ariane) open-source RISC-V core.

   Assembly

2. DDR-Multi-Channel-Memory-Controller DDR-Multi-Channel-Memory-Controller Public

   Multi-Channel DDR Memory Controller Design with BFM-Based Verification and UVM-Style Testbench

   Verilog 10 3

3. 16x16_systolic-array-processor 16x16_systolic-array-processor Public

   systolic_array_processor for CNN, DNN, GEMM (16x16 PE array)

   Verilog 7 2

4. Preprocessing_Accelerator_for_Frequency_domain_based_CNN_Models Preprocessing_Accelerator_for_Frequency_domain_based_CNN_Models Public

   Preprocessing_Accelerator for Frequency domain CNN model

   Verilog 1

5. openhwgroup/cva6 openhwgroup/cva6 Public

   The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

   Assembly 3.1k 1k