FazBrowse GitHub Viewer | Trending |
URL:
| Home
Tools: [Download Repo ZIP]   [Original HTTPS Page]

utility: support automatic low-speed clock detection by haydenth · Pull Request #90 · stm32duino/STM32duinoBLE · GitHub

/ STM32duinoBLE Public
forked from arduino-libraries/ArduinoBLE

utility: support automatic low-speed clock detection #90

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
fpistm merged 1 commit into from
Aug 12, 2026
Conversation 3 Commits 1 Checks 5 Files changed
Merged

utility: support automatic low-speed clock detection #90

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension .cpp  (1) All 1 file type selected
Viewed files
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Unified
Split
Hide whitespace
Diff view
Unified
Split
Hide whitespace
48 changes: 31 additions & 17 deletions src/utility/HCISharedMemTransport.cpp
Show comments
View file
Open in desktop
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters. Learn more about bidirectional Unicode characters
Show hidden characters
Original file line number Diff line number Diff line change
Expand Up @@ -572,26 +572,40 @@ size_t HCISharedMemTransportClass::write(const uint8_t *data, size_t length)
//private:
void HCISharedMemTransportClass::start_ble_rf(void)
{
/* Set the DBP bit in the Power control register 1 (PWR_CR1) */
LL_PWR_EnableBkUpAccess();

/* LSE belongs to the back-up domain, enable access.*/
while (!LL_PWR_IsEnabledBkUpAccess()) {
/* Wait for Backup domain access */
}
LL_RCC_ForceBackupDomainReset();
LL_RCC_ReleaseBackupDomainReset();
/* Read the actual configured RF Wakeup clock source from registers */
uint32_t rfwkpSource = LL_RCC_GetRFWKPClockSource();

if (rfwkpSource == LL_RCC_RFWKP_CLKSOURCE_LSE) {
/* LSE is selected: Enable LSE and wait for ready */
LL_PWR_EnableBkUpAccess();
while (!LL_PWR_IsEnabledBkUpAccess()) {
/* Wait for Backup domain access */
}
LL_RCC_ForceBackupDomainReset();
LL_RCC_ReleaseBackupDomainReset();

/* Enable LSE Oscillator (32.768 kHz) */
LL_RCC_LSE_Enable();
while (!LL_RCC_LSE_IsReady()) {
/* Wait for LSE ready */
}
LL_RCC_LSE_Enable();
while (!LL_RCC_LSE_IsReady()) {
/* Wait for LSE ready */
}

LL_PWR_DisableBkUpAccess();
LL_PWR_DisableBkUpAccess();

/* Switch OFF LSI as LSE is the source clock */
LL_RCC_LSI2_Disable();
/* Switch OFF LSI as LSE is the source clock */
LL_RCC_LSI2_Disable();
}
#if defined(LL_RCC_RFWKP_CLKSOURCE_LSI)
else if (rfwkpSource == LL_RCC_RFWKP_CLKSOURCE_LSI) {
/* LSI is selected: Enable LSI1 and wait for ready */
LL_RCC_LSI1_Enable();
while (!LL_RCC_LSI1_IsReady()) {
/* Wait for LSI1 ready */
}
}
Comment thread
fpistm marked this conversation as resolved.
#endif
else if (rfwkpSource == LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024) {
/* HSE/1024 is selected: No low-speed oscillator needs enabling */
}
}

void HCISharedMemTransportClass::stm32wb_reset(void)
Expand Down
Loading
Back | FazBrowse Home | New Git URL