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functional-simulation

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yonseicasl / NPUsim

NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators

machine-learning acceleration simulator deep-learning memory model accelerator architecture modeling hierarchy cycle-accurate deep-neural-network npu hardware-accelerator full-system value-aware functional-simulation timing-simulation

Updated Aug 28, 2026
C++

DivyamGoyal-github / RISC_V-SoC-Tapeout-Program_VSD_Caravel_IITGN_Phase2

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This repository contains documentation and relevant materials for the RISC-V SoC Tapeout Program, a collaborative initiative between IIT Gandhinagar, VLSI System Design (VSD), and other prominent organizations in the field of semiconductor design.

simulation verification rtl verilog gls synopsys risc-v caravel pdk chip-design functional-simulation scl180nm

Updated Jan 5, 2026
Verilog

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