Pull requests

• update for chipsalliance/chisel3#1944

  #318·sequencer opened Jul 11, 2021Member·

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  1

• Support for FST traces in verilator backend

  #250·kammoh opened Jun 24, 2019·

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  3

• Import build flags from environment (a la Chisel2).

  #245·ucbjrl opened May 3, 2019Contributor·

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  5

• [WiP]: Loading verilator as shared libraries

  #233·grebe opened Feb 25, 2019Contributor·

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  15

• Add IntermediateBackend for generating verilog testbenches

  #138·grebe opened Apr 11, 2017Contributor·

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  2

• verilator DUT cpp generation bug

  #135·stevobailey opened Mar 23, 2017·

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  1

• Use IrrevocableIO for sink in AdvTester, reflecting assumptions

  #81·albert-magyar opened Jan 11, 2017Contributor·

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