This PR addresses issue #140 by documenting the current status and limitations of the W (processing width) parameter through synthesis testing and code analysis.

Changes

• Added docs/W_PARAMETER.md documenting W parameter status, testing results, and known limitations
• Updated README.md to reference W parameter documentation in new Parameters section
• Documented W=1 (bit-serial) as the only currently supported configuration
• Identified specific source files (serv_csr.v, serv_immdec.v) with hardcoded indices preventing W>1 support

Testing

Synthesis testing performed using Vivado 2025.1 targeting Artix-7 xc7a35tcpg236-1:

• W=1: 173 LUTs (0.83%), 182 registers (0.44%) - fully functional
• W>1: Infrastructure exists but hardcoded bit indices cause synthesis warnings and non-functional designs

The W parameter infrastructure is present throughout the codebase, but implementation is incomplete. Referenced qerv as a working 4-bit implementation for future contributors.

Closes #140