HORNET-RV32IMF is an academic-grade, 5-stage pipelined RISC-V soft-core processor designed for high-efficiency floating-point arithmetic and Edge AI applications. It implements the RV32IMF Instruction Set Architecture (ISA) and is optimized for deployment across Xilinx Artix-7 platforms, including the Nexys Video and Nexys-4-DDR.

This project is the result of collaborative engineering at the Istanbul Technical University (ITU) and the GSTL Lab.

• Prof. Dr. Sıddıka Berna Örs Yalçın - ITU Academic Profile

• Yavuz Selim Tozlu - GitHub
• Yasin Yılmaz - GitHub

• Salih Daysal
• Mehmet Emin Tuzcu

• Deniz Zakir Eroglu - GitHub
• Mete Kaan Özden - GitHub

• Deniz Zakir Eroglu - GitHub
• Yusuf Tekin - GitHub

• Yusuf Tekin & Ahmet Tolga Özkan- 🔗 HORNET-RV32IMF-For-AI-Applications

The initial design of Hornet core is detailed in the following conference paper:

Y. S. Tozlu, Y. Yilmaz, B. Ors, “Design and Implementation Of a 32-Bit RISC-V Core”, 12th International Conference on Electrical and Electronics Engineering (ELECO), 2021.

The verification methodologies used in this core are detailed in the following conference paper:

D. Z. Eroglu, M. K. Ozden, B. Ors, “Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools”, 9th International Symposium on Multidisciplinary Studies and Innovative Technologies (ISMSIT), 2025.

• Toolchain: riscv32-unknown-elf-gcc (RV32IMF / ILP32F)
• Simulation: Vivado Simulator / Verilator
• Python: 3.x (with pyserial for hardware-in-the-loop tests)

• FPGA: Nexys-4-DDR (Artix-7 100t) or Nexys Video (Artix-7 200t)
• Vivado Version: Verified on Vivado 2025.2

• source/: RTL Verilog files for the core, FPU, and Wishbone peripherals.
• drivers/: Bare-metal C drivers for UART, GPIO, and Interrupt handling.
• test/: Comprehensive test suites including FPU arithmetic, Bubble Sort, and MLP Neural Network inference.
• rom_gen/: Custom tools to convert compiled binaries into FPGA-ready .mem files.

1. Generate Firmware: Navigate to test/gpio or test/uart-fpu-fpga and run make build.
2. Synthesis: Load the source/ files into Vivado 2025.2. Ensure the generated memory_init.mem is linked to the BRAM initialization.
3. Deploy: Program the Nexys-4-DDR and monitor the output via the USB-UART bridge (Baud: 115200).

For technical inquiries or bug reports, please open an issue in this repository or contact the organizers:

• Yusuf Tekin: tekiny20@itu.edu.tr - GitHub Profile
• Deniz Zakir Eroglu: eroglud20@itu.edu.tr - GitHub Profile

Developed at Istanbul Technical University. 🐝