esp32でmmd

IEEE 754 single and double precision floating point library in systemverilog and vhdl

Chisel library for Unum Type-III Posit Arithmetic

IEEE 754 single precision floating point library in systemverilog and vhdl

Wrappers for open source FPU hardware implementations.

NoeticMaze is the embedded control and navigation project used for the NUCLEO-F446RE demonstration. The system integrates lidar, IMU, wheel encoders, differential-drive motor control, ICP-based localisation, grid mapping, A* path planning, path following, Bluetooth telemetry, and FreeRTOS task scheduling.

A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA

Research enablement kit for designing and prototyping a Cortex-M0–based SoC with custom IP integration (education, research)

Pure Rust port of Berkeley Softfloat, mostly const

A chisel3 wrapper for pulp-platform/fpnew

A 5-stage pipelined RV32IMF RISC-V SoC optimized for FPGA (Nexys Video/4-DDR). Features a custom IEEE-754 FPU, interrupt-driven UART, and various peripherals.

This repository contains an assembly program written in AT&T syntax called FPU-Analyzer. The program analyzes a series of floating-point numbers and calculates their sum and average.

X86-64 bilateral instruction tokenizer implemented in C. Supports the following processor extensions: AES, AVX, AVX2, AVX512, FMA, MMX, SSE, SSE2, SSE3, SSE4, x87(FPU), VMX. In order to ease testing, a diassembler which transforms tokens into compilable assembly (for NASM compiler) has been implemented.

Laboratory works with Assembly x86 (NASM) using Linux.

IEEE 754 single-precision FPU (add/sub/mul) — lightweight Verilog implementation.

SH4 XMTRX viewer

IEEE-754 Compliant Floating Point Unit (FPU)

drivers for multiple peripheral of the SAME70Q21 made for the XPLD board

Mirror of VFLOAT from https://coe.northeastern.edu/Research/rcl/projects/floatingpoint/index.html

Bug fixes for OpenCores fpu100 multiplier (bugtracker #2/#4/#5). HW verified on Cyclone V.