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Karan-nevage (Karankumar Nevage) · GitHub

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karan-nevage/README.md
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Hi, I'm Karankumar Nevage 👋

Frontend VLSI Design & Verification Engineer

A passionate and results-driven Design Verification professional with a strong foundation in UVM methodology and digital design principles. My focus is on creating robust and reusable testbenches to ensure the quality and reliability of hardware products.

💻 Technical Skills

  • Languages: System Verilog, Verilog, C, C++, Python
  • Methodologies & Tools: UVM, Synopsys VCS, Synopsys Verdi, QuestaSim, Vivado, Git, Linux
  • Protocols: AXI, AHB, APB, I2C, SPI
  • Concepts: RTL Designing, Design Verification, Functional Coverage, Assertion-Based Verification

✨ Featured Projects

✤ AXI Universal Verification Component (UVC) (View Repo)
✤ APB Protocol UVM Based Verification (View Repo)
✤ Asynchronous FIFO Design and Verificationn (View Repo)
✤ Memory UVM Based Verification (Single Port RAM) (View Repo)
✤ Automatic Washing Mashine Controller (View Repo)
✤ Full Adder UVM Verification (View Repo)
✤ Single Cycle RISC-V Processor Implementation (View Repo)
✤ APB Protocol Implementation (View Repo)
✤ Nexas A7 Accelerometer (View Repo)

🧩 VLSI Community Contribution

✦ HDL Bits Solutions (↪View Contribtion)
✦ Beginer Verilog Program (↪View Contribtion)
✦ SystemVerilog Pattern Generations (↪View Contribtion)

GitHub Stats

Connect with Me

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  1. AXI-UVC AXI-UVC Public

    Reusable AXI Universal Verification Component built with SystemVerilog and UVM. Integrates into any testbench to accelerate design verification with modular agents, monitors, drivers, coverage, and…

    SystemVerilog 2

  2. Memory-UVM-Verification Memory-UVM-Verification Public

    This project provides a comprehensive verification framework for a synchronous single-port RAM module implemented in Verilog. The memory module is configurable with parameters for data width, memor…

    SystemVerilog

  3. APB-Protocol-UVM-Based-Verification APB-Protocol-UVM-Based-Verification Public

    APB protocol verification using UVM. Includes APB interface, driver, monitor, responder, and scoreboard. Supports read/write transactions, constrained randomization, coverage, and error injection. …

    SystemVerilog

  4. Asynchronous-FIFO-Design-and-Verification Asynchronous-FIFO-Design-and-Verification Public

    This repository contains an asynchronous FIFO design and a comprehensive UVM testbench for its functional verification. It demonstrates a robust, real-world approach to digital design and verificat…

    SystemVerilog 3

  5. Nexys-A7-Accelerometer-FPGA Nexys-A7-Accelerometer-FPGA Public

    This project showcases the integration of a 3-axis accelerometer (ADXL362) with the Nexys A7-50T FPGA board. The accelerometer data is read via SPI communication and displayed on 7-segment displays…

    Verilog 3 1

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