SystemVerilog-Pattern-Generation-Interview-Questions
This repository contains solved SystemVerilog pattern generation problems commonly asked in technical interviews. It includes documented code, problem statements, and testbenches to help engineers master pattern generation techniques, such as sequences, randomization, and constraints, for interview preparation.
Advice: Try solving the problems in the questions/ folder on your own first. If you get stuck, refer to the solutions in the solutions/ folder for guidance.
- Access the EDA Playground link for the desired set from the Solution Links section.
- In the EDA Playground project, open design.sv.
- Modify the include directive in design.sv to select the desired question by changing the line:
- For Question 1, use `include "que_01.sv".
- For Question 2, use `include "que_02.sv".
- Select QuestaSim or any compatible SystemVerilog simulator as the tool.
- Set the language to SystemVerilog.
- Click Run to execute and view the output in the console.
- Copy the solution code from solutions/Solution_Set-XX/que_XX.sv (e.g., solutions/Solution_Set-02/que_03.sv).
- Copy testbench.sv from the repository root.
- Modify testbench.sv to include the desired question (e.g., `include "Solution_Set-02/que_03.sv").
- Compile and run using a SystemVerilog simulator (e.g., QuestaSim, VCS) in your local environment.
- Check the console for the output.
Contributions are welcome! Follow these steps:
- Add new questions to questions/Question_Set-XX/ (e.g., que_XX.sv).
- Provide corresponding solutions in solutions/Solution_Set-XX/ (e.g., que_XX.sv).
- Ensure proper formatting, technical comments, and attribution in all files.
- Update testbench.sv comments with new question references.
- Submit a pull request with a clear description of your additions.
🧠 Question Set-01: Combination of 0 and 1 Pattern Questions
| Question No. |
Pattern Description |
| 1 |
Generate the pattern 0 1 0 2 0 3 0 4 0 5 |
| 2 |
Generate the pattern {010011000111} |
| 3 |
Generate the pattern {110011001100} |
| 4 |
Generate the pattern {111000111000} |
| 5 |
Generate the pattern {01010101} |
| 6 |
Generate the pattern {001100110011} |
| 7 |
Generate the pattern {000111000111} |
This repository is licensed under the Apache License 2.0. See LICENSE for details.