A SystemVerilog implementation of an advanced 64-bit RISC-V processor, developed from the RTL foundations upward toward a pipelined, speculative, superscalar, and eventually out-of-order microarchitecture.

The project focuses on building a processor from the hardware level: individual RTL components are designed and verified first, then progressively integrated into datapaths, control logic, pipelines, memory systems, and ultimately an advanced processor architecture.

Project development started: August 2026.

This project is being developed incrementally rather than as a single monolithic CPU.

The development progression is:

1. RTL and SystemVerilog fundamentals
2. Combinational hardware building blocks
3. Sequential and stateful hardware
4. RV64 datapath and control
5. Five-stage pipelined processor
6. Hazard detection and forwarding
7. Branch prediction
8. Cache and memory subsystem
9. Speculative execution
10. Register renaming
11. Dynamic scheduling
12. Out-of-order execution
13. Precise retirement and recovery
14. FPGA implementation and evaluation

Each major subsystem is designed, simulated, verified, and integrated progressively.

The long-term processor target is an advanced 64-bit RISC-V implementation with:

• RV64 architecture
• RV64GC-oriented support
• Five-stage in-order pipeline as the initial processor
• Superscalar execution
• Dynamic branch prediction
• Instruction and data caches
• Register renaming
• Physical register file
• Reservation stations / issue queues
• Tomasulo-style dynamic scheduling
• Reorder buffer
• Speculative execution
• Precise exception handling
• In-order retirement
• FPGA-oriented implementation

The architecture is intentionally developed in stages so that each major component can be independently verified before becoming part of the complete processor.

The processor is built from the bottom up.

The project begins with small synthesizable RTL components such as:

• Logic gates
• Bus and signal manipulation
• Multiplexers and decoders
• Encoders
• Arithmetic units
• Comparators
• Shifters
• ALUs
• Parameterized RTL components

These components are then used to construct increasingly complex processor-oriented hardware including:

• RV64 instruction decoding
• Immediate generation
• Branch and PC logic
• Load/store datapath components
• Register files
• Pipeline infrastructure
• Memory structures
• FIFOs
• Hazard handling
• Branch prediction
• Cache structures
• Dynamic scheduling
• Out-of-order execution

The objective is not simply to produce a working CPU, but to understand and implement the underlying microarchitecture at the RTL level.

The project is currently focused on building the RTL foundation and RV64 processor infrastructure.

Current areas include:

• SystemVerilog RTL design
• Boolean and combinational logic
• Signal and bus operations
• Data selection and routing
• Arithmetic building blocks
• Comparison and decision logic
• Shifters
• Parameterized RTL
• Verification and testbenches
• Vivado design flow
• RV64 instruction decoding
• RV64 immediate generation
• RV64 datapath components

Development will progressively move from combinational RTL into sequential hardware, pipelining, memory systems, and advanced processor microarchitecture.

Processor-specific RTL includes:

• RISC-V instruction field extraction
• R-type instructions
• I-type instructions
• S-type instructions
• B-type instructions
• U-type instructions
• J-type instructions
• Immediate generation
• Instruction classification
• RV64I decoding
• ALU control
• Branch control
• Load/store control
• PC generation
• Branch target calculation
• JAL/JALR target generation
• Address generation
• Load-data extraction
• Store-data alignment

These components will eventually form the front end and datapath of the processor.

Verification is performed progressively at module, subsystem, and processor level.

RTL modules are tested using dedicated SystemVerilog testbenches.

Testing includes:

• Directed test cases
• Boundary conditions
• Corner cases
• Randomized inputs
• Expected-result checking
• Waveform analysis
• RTL debugging

As modules are integrated, verification expands to:

• Datapath verification
• Control-path verification
• Register-file verification
• Pipeline verification
• Memory-system verification
• Branch-prediction verification
• Processor-level testing

The final processor will be tested using:

• RISC-V instruction sequences
• Assembly programs
• Compiled programs
• Reference-model comparison
• Regression testing
• Performance measurements

Primary tools used throughout the project include:

• SystemVerilog
• Icarus Verilog
• vvp
• Git
• GitHub
• Vivado
• RISC-V toolchain
• FPGA development tools

Additional tools may be introduced as the architecture develops.

The project is intended to develop practical expertise in:

• RTL design
• SystemVerilog
• Digital logic
• Computer architecture
• Processor microarchitecture
• Hardware verification
• FPGA implementation
• Pipeline design
• Memory systems
• Branch prediction
• Speculative execution
• Dynamic scheduling
• Out-of-order execution

Particular emphasis is placed on writing synthesizable RTL, understanding the hardware inferred from that RTL, and verifying each component before integration.

As the processor develops, implementations will be evaluated using metrics including:

• Maximum clock frequency
• Timing slack
• CPI
• IPC
• Instruction throughput
• LUT utilization
• Flip-flop utilization
• BRAM utilization
• DSP utilization
• Branch prediction accuracy
• Cache hit rate
• Pipeline stalls
• Pipeline flushes

Architectural and RTL trade-offs will be evaluated using both functional correctness and implementation results.

1. SystemVerilog & RTL Foundations
2. Combinational Hardware
3. Sequential Hardware
4. RV64 Datapath & Control
5. Five-Stage Pipeline
6. Hazard Detection & Forwarding
7. Branch Prediction
8. Cache & Memory Subsystem
9. Speculative Execution
10. Register Renaming
11. Dynamic Scheduling
12. Out-of-Order Execution
13. Precise Retirement & Recovery
14. FPGA Validation

The roadmap is intentionally incremental. Major architectural features are introduced only after the underlying hardware has been implemented and verified independently.