Library for specialized dense and sparse matrix operations, and deep learning primitives.

Simple risc-v emulator, able to run linux, written in C.

RISC-V emulator in Rust that boots Linux with JIT on ARM64/x86_64 and Sv39 virtual memory

Lightweight and performant dynamic binary translation for RISC–V code on x86–64

A pure Java implementation of a 64-bit user-space RISC-V emulator.

RV64GC interpreter written in Rust

Arch Linux RISC-V images for Banana Pi F3 with SpacemiT K1 / M1 / X60.

Taurus 3001 RISC-V 64-bit Privileged Minimal System Processor for T110/T28 ASIC

A RISC-V (RV64) emulator written in Rust.

PasRISCV is a RV64GCV/RVA23 RISC-V emulator, which is implemented in Object Pascal

The PasVulkan-based emulator frontend for the PasRISCV RV64GC RISC-V emulator

A riscv emulator that can run linux

Design guidelines and performance analysis for 10 RISC-V 5- to 8-stage pipeline variants based on basic_RV32S and IMA_make_RV64, covering ISA extension scaling, pipeline-depth sweep, and 100 MHz(125) timing closure on Artix-7 FPGA.

RV64GC RISC-V emulator written in Go capable of booting Linux, NetBSD, and FreeBSD with OpenSBI, U-Boot, SV39 virtual memory, and VirtIO devices.

Zak's New(-ish) C(-ish) Compiler

Learning OS development with Rust and RISC-V. A minimalist, well-documented kernel exploring memory management, low-level hardware abstraction, and bare-metal systems programming.

A RISC-V rv64ima_zicsr_zifencei emulator.

Common types for assembly architectures

fast rv64im emulator for web

Design and implementation of an advanced 64-bit RISC-V processor in SystemVerilog, progressing from a pipelined in-order core toward an out-of-order architecture with dynamic scheduling, branch prediction, caches, register renaming, and precise retirement.