Lightweight and performant dynamic binary translation for RISC–V code on x86–64

JIT-accelerated RISC-V instruction set simulator

A System Level RISCV32 Emulator Over x86_64: capable of booting RISCV Linux

Ratel - a new framework for instruction-level interposition on enclaved applications

x86 to ARM64 translator

A from-scratch Android native bridge that JIT-translates ARM64 shared libraries to x86-64 at load time.

Dynamic binary translator from ARM Cortex-M architecture to WebAssembly. University project.

Z80 + CP/M dynamic binary translator — 4.3 billion Z80 instructions/sec on Apple Silicon, verified against a lockstep interpreter