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instruction-decoding

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LekKit / RVVM

Star 1.3k

The RISC-V Virtual Machine

c linux emulator vm translation virtual-machine emulation jit riscv risc emulators risc-v riscv32 riscv-linux riscv64 tracing-jit riscv-simulator riscv-emulator instruction-decoding rvvm
  • Updated Aug 13, 2026
  • C

DispatchCode / x64-Instruction-Decoder

Star 36

An x86/x64 instruction disassembler written in C

c assembly x64 reverse-engineering disassembler x86 low-level machine-code instruction-set architectures disassembler-library instruction-decoding
  • Updated Aug 19, 2026
  • C

OPSphystech420 / CGuardProbe

Star 15

Memory Engine and Scanner for iOS/MacOS using Mach API

macos api hooks security ios cpp memory reverse-engineering mach-o ida memory-scanning error-logging instruction-decoding vmt-hooking
  • Updated Nov 16, 2024
  • C++

Danijel-Korent / RISC-V-emulator

Star 12

RISC-V emulator/simulator in Python

python education processor-architecture cpu python3 riscv bare-metal risc-v baremetal cpu-simulator riscv32 riscv-linux riscv-simulator riscv-emulator rv32ima instruction-decoding risc-v-emulator risc-v-simulator system-emulation
  • Updated Aug 25, 2025
  • Python

BeRo1985 / pasriscv

Sponsor
Star 6

PasRISCV is a RV64GCV/RVA23 RISC-V emulator, which is implemented in Object Pascal

emulator delphi pascal vm virtual-machine freepascal riscv emulators risc-v object-pascal virtio riscv-linux riscv64 rv64gc rv64 instruction-decoding rv64gcv rva23
  • Updated Aug 14, 2026
  • Pascal

BeRo1985 / pasriscvemu

Sponsor
Star 5

The PasVulkan-based emulator frontend for the PasRISCV RV64GC RISC-V emulator

emulator delphi pascal vm virtual-machine vulkan freepascal riscv emulators risc-v object-pascal virtio riscv-linux riscv64 riscv-emulator rv64gc rv64 instruction-decoding
  • Updated Aug 14, 2026
  • Pascal

gaidardzhiev / tortoise

Star 3

Custom CPU emulator and assembler

assembler assembly-language instruction-set-architecture cpu-emulator cpu-architecture fetch-decode-execute bitwise-operations instruction-decoding emulator-development cpu-architecture-design
  • Updated Apr 23, 2026
  • C

leonlafa / sap1-logisim

Star 2

A simulation of a Simple-As-Possible (SAP) computer, implemented in Logisim Evolution.

ram binary electronics logic-gates alu 8bit sap1 registers digital-electronics memory-address program-counter electronics-engineering full-adder control-sequences sap-1 arithmetic-logic-unit bus-system 8bitcomputer instruction-decoding sap-1-computer
  • Updated May 26, 2025

keneoneth / InstrHexBinDecConvertDecoder-Release

Star 1

a web based front end only helper tool that provides Instruction Decoder and Converter in hexadecimal binary decimal form encoding of different ISA

instructions opcodes instruction-set-architecture binary-hexadecimal-converter binary-to-decimal-number-converter instruction-decoding
  • Updated Feb 6, 2023
  • HTML

chgroeling / armv7m-decoder

Star 0

ARMv7-M (Thumb) instruction decoder and disassembler in Python - full instruction set, objdump-compatible output, generated from a YAML spec.

python arm embedded cortex-m reverse-engineering code-generation armv7m objdump thumb dissassembler firmware-analysis instruction-decoding
  • Updated Aug 4, 2026
  • Python

christalphilip / mips-disassembler

Star 0

A Java-based MIPS disassembler that converts binary machine code into readable MIPS assembly instructions, supporting key R- and I-format instructions with branch target address resolution.

java mips assembly disassembler computer-architecture instruction-decoding
  • Updated Jul 31, 2025
  • Java

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